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| author | Thomas Huth <thuth@redhat.com> | 2024-10-11 15:19:33 +0200 |
|---|---|---|
| committer | Thomas Huth <thuth@redhat.com> | 2024-10-21 16:40:11 +0200 |
| commit | 68ad89b75ad2bb5f38abea815a50ec17a142565a (patch) | |
| tree | 4d24d0bdcc384d91ebcc515bbc23a8680a128292 /tests/functional/test_riscv32_tuxrun.py | |
| parent | 9ca8239aad94c1da9c8a2423a7c983cf5febfd32 (diff) | |
| download | focaccia-qemu-68ad89b75ad2bb5f38abea815a50ec17a142565a.tar.gz focaccia-qemu-68ad89b75ad2bb5f38abea815a50ec17a142565a.zip | |
Revert "hw/sh4/r2d: Realize IDE controller before accessing it"
This reverts commit 3c5f86a22686ef475a8259c0d8ee714f61c770c9. Changing the order here caused a regression with the "tuxrun" kernels (from https://storage.tuxboot.com/20230331/) - ATA commands fail with a "ata1: lost interrupt (Status 0x58)" message. Apparently we need to wire the interrupt here first before realizing the device, so revert the change to the original behavior. Reported-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241011131937.377223-17-thuth@redhat.com>
Diffstat (limited to 'tests/functional/test_riscv32_tuxrun.py')
0 files changed, 0 insertions, 0 deletions