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authorShuuichirou Ishii <ishii.shuuichir@fujitsu.com>2021-08-31 17:29:40 +0900
committerPeter Maydell <peter.maydell@linaro.org>2021-09-01 11:08:18 +0100
commit499243e189429d3e5a0572be14ed2f98251e38a1 (patch)
treeff20a91ffa3a2bcfb0340f5c7810f33a9c783236 /tests/qtest/arm-cpu-features.c
parent4d39fcd8af11c0395d7b5112828d65d48cf0cfae (diff)
downloadfocaccia-qemu-499243e189429d3e5a0572be14ed2f98251e38a1.tar.gz
focaccia-qemu-499243e189429d3e5a0572be14ed2f98251e38a1.zip
tests/arm-cpu-features: Add A64FX processor related tests
Add tests that the A64FX CPU model exposes the expected features.

Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
[PMM: added commit message body]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/qtest/arm-cpu-features.c')
-rw-r--r--tests/qtest/arm-cpu-features.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 8252b85bb8..90a87f0ea9 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -473,6 +473,19 @@ static void test_query_cpu_model_expansion(const void *data)
         assert_has_feature_enabled(qts, "cortex-a57", "pmu");
         assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
 
+        assert_has_feature_enabled(qts, "a64fx", "pmu");
+        assert_has_feature_enabled(qts, "a64fx", "aarch64");
+        /*
+         * A64FX does not support any other vector lengths besides those
+         * that are enabled by default(128bit, 256bits, 512bit).
+         */
+        assert_has_feature_enabled(qts, "a64fx", "sve");
+        assert_sve_vls(qts, "a64fx", 0xb, NULL);
+        assert_error(qts, "a64fx", "cannot enable sve384",
+                     "{ 'sve384': true }");
+        assert_error(qts, "a64fx", "cannot enable sve640",
+                     "{ 'sve640': true }");
+
         sve_tests_default(qts, "max");
         pauth_tests_default(qts, "max");