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authorPeter Maydell <peter.maydell@linaro.org>2019-03-05 21:07:29 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-03-05 21:07:29 +0000
commitb5b6b2b912bbcd3953407da938a8f969577ad3a1 (patch)
tree57900df799ddbb06c25c34bf0a90842646806f63 /tests/tcg/mips/include
parenta3e3b0a7bd5de211a62cdf2d6c12b96d3c403560 (diff)
parent0fdd986a6c8f921693d025c3f095a0eaf628b6b6 (diff)
downloadfocaccia-qemu-b5b6b2b912bbcd3953407da938a8f969577ad3a1.tar.gz
focaccia-qemu-b5b6b2b912bbcd3953407da938a8f969577ad3a1.zip
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-mar-05-2019' into staging
MIPS queue for March 5th, 2019

# gpg: Signature made Tue 05 Mar 2019 16:06:34 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-mar-05-2019:
  target/mips: Add tests for integer add MSA instruction group
  tests/tcg: target/mips: Add tests for MSA pack instructions
  tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructions
  tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions
  tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions
  tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions
  tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions
  tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions
  tests/tcg: target/mips: Extend functionality of MSA wrapper macros
  tests/tcg: target/mips: Fix test utilities for 128-bit tests
  tests/tcg: target/mips: Add test utilities for 64-bit tests
  tests/tcg: target/mips: Add test utilities for 32-bit tests
  tests/tcg: target/mips: Add wrappers for various MSA instructions
  disas: nanoMIPS: Add graphical description of pool organization
  disas: nanoMIPS: Correct comments to handlers of some DSP instructions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/tcg/mips/include')
-rw-r--r--tests/tcg/mips/include/test_inputs.h4
-rw-r--r--tests/tcg/mips/include/test_inputs_32.h122
-rw-r--r--tests/tcg/mips/include/test_inputs_64.h208
-rw-r--r--tests/tcg/mips/include/test_utils.h15
-rw-r--r--tests/tcg/mips/include/test_utils_32.h78
-rw-r--r--tests/tcg/mips/include/test_utils_64.h78
-rw-r--r--tests/tcg/mips/include/wrappers_mips64r6.h83
-rw-r--r--tests/tcg/mips/include/wrappers_msa.h121
8 files changed, 700 insertions, 9 deletions
diff --git a/tests/tcg/mips/include/test_inputs.h b/tests/tcg/mips/include/test_inputs.h
index c173d589ff..5406e4e2df 100644
--- a/tests/tcg/mips/include/test_inputs.h
+++ b/tests/tcg/mips/include/test_inputs.h
@@ -28,7 +28,7 @@
 #define PATTERN_INPUTS_COUNT          64
 #define PATTERN_INPUTS_SHORT_COUNT     8
 
-uint64_t b128_pattern[PATTERN_INPUTS_COUNT][2] = {
+static const uint64_t b128_pattern[PATTERN_INPUTS_COUNT][2] = {
     { 0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL, },   /*   0 */
     { 0x0000000000000000ULL, 0x0000000000000000ULL, },
     { 0xAAAAAAAAAAAAAAAAULL, 0xAAAAAAAAAAAAAAAAULL, },
@@ -99,7 +99,7 @@ uint64_t b128_pattern[PATTERN_INPUTS_COUNT][2] = {
 #define RANDOM_INPUTS_COUNT           16
 #define RANDOM_INPUTS_SHORT_COUNT      4
 
-uint64_t b128_random[RANDOM_INPUTS_COUNT][2] = {
+static const uint64_t b128_random[RANDOM_INPUTS_COUNT][2] = {
     { 0x886AE6CC28625540ULL, 0x4B670B5EFE7BB00CULL, },   /*   0 */
     { 0xFBBE00634D93C708ULL, 0x12F7BB1A153F52FCULL, },
     { 0xAC5AAEAAB9CF8B80ULL, 0x27D8C6FFAB2B2514ULL, },
diff --git a/tests/tcg/mips/include/test_inputs_32.h b/tests/tcg/mips/include/test_inputs_32.h
new file mode 100644
index 0000000000..a3b7e5464a
--- /dev/null
+++ b/tests/tcg/mips/include/test_inputs_32.h
@@ -0,0 +1,122 @@
+/*
+ *  Header file for pattern and random test inputs
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef TEST_INPUTS_32_H
+#define TEST_INPUTS_32_H
+
+#include <stdint.h>
+
+
+#define PATTERN_INPUTS_32_COUNT          64
+#define PATTERN_INPUTS_32_SHORT_COUNT     8
+
+static const uint32_t b32_pattern[PATTERN_INPUTS_32_COUNT] = {
+    0xFFFFFFFF,                                          /*   0 */
+    0x00000000,
+    0xAAAAAAAA,
+    0x55555555,
+    0xCCCCCCCC,
+    0x33333333,
+    0xE38E38E3,
+    0x1C71C71C,
+    0xF0F0F0F0,                                          /*   8 */
+    0x0F0F0F0F,
+    0xF83E0F83,
+    0x07C1F07C,
+    0xFC0FC0FC,
+    0x03F03F03,
+    0xFE03F80F,
+    0x01FC07F0,
+    0xFF00FF00,                                          /*  16 */
+    0x00FF00FF,
+    0xFF803FE0,
+    0x007FC01F,
+    0xFFC00FFC,
+    0x003FF003,
+    0xFFE003FF,
+    0x001FFC00,
+    0xFFF000FF,                                          /*  24 */
+    0x000FFF00,
+    0xFFF8003F,
+    0x0007FFC0,
+    0xFFFC000F,
+    0x0003FFF0,
+    0xFFFE0003,
+    0x0001FFFC,
+    0xFFFF0000,                                          /*  32 */
+    0x0000FFFF,
+    0xFFFF8000,
+    0x00007FFF,
+    0xFFFFC000,
+    0x00003FFF,
+    0xFFFFE000,
+    0x00001FFF,
+    0xFFFFF000,                                          /*  40 */
+    0x00000FFF,
+    0xFFFFF800,
+    0x000007FF,
+    0xFFFFFC00,
+    0x000003FF,
+    0xFFFFFE00,
+    0x000001FF,
+    0xFFFFFF00,                                          /*  48 */
+    0x000000FF,
+    0xFFFFFF80,
+    0x0000007F,
+    0xFFFFFFC0,
+    0x0000003F,
+    0xFFFFFFE0,
+    0x0000001F,
+    0xFFFFFFF0,                                          /*  56 */
+    0x0000000F,
+    0xFFFFFFF8,
+    0x00000007,
+    0xFFFFFFFC,
+    0x00000003,
+    0xFFFFFFFE,
+    0x00000001,
+};
+
+
+#define RANDOM_INPUTS_32_COUNT           16
+#define RANDOM_INPUTS_32_SHORT_COUNT      4
+
+static const uint32_t b32_random[RANDOM_INPUTS_32_COUNT] = {
+    0x886AE6CC,                                          /*   0 */
+    0xFBBE0063,
+    0xAC5AAEAA,
+    0x704F164D,
+    0xB9926B7C,
+    0xD027BE89,
+    0xB83B5806,
+    0xFC8F23F0,
+    0x201E09CD,                                          /*   8 */
+    0xA57CD913,
+    0xA2E8F6F5,
+    0xA89CF2F1,
+    0xE61438E9,
+    0x944A35FD,
+    0x46304263,
+    0x8B5AA7A2,
+};
+
+
+#endif
diff --git a/tests/tcg/mips/include/test_inputs_64.h b/tests/tcg/mips/include/test_inputs_64.h
new file mode 100644
index 0000000000..6891a362a3
--- /dev/null
+++ b/tests/tcg/mips/include/test_inputs_64.h
@@ -0,0 +1,208 @@
+/*
+ *  Header file for pattern and random test inputs
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef TEST_INPUTS_64_H
+#define TEST_INPUTS_64_H
+
+#include <stdint.h>
+
+
+#define PATTERN_INPUTS_64_COUNT          64
+#define PATTERN_INPUTS_64_SHORT_COUNT     8
+
+static const uint64_t b64_pattern[PATTERN_INPUTS_64_COUNT] = {
+    0xFFFFFFFFFFFFFFFFULL,                               /*   0 */
+    0x0000000000000000ULL,
+    0xAAAAAAAAAAAAAAAAULL,
+    0x5555555555555555ULL,
+    0xCCCCCCCCCCCCCCCCULL,
+    0x3333333333333333ULL,
+    0xE38E38E38E38E38EULL,
+    0x1C71C71C71C71C71ULL,
+    0xF0F0F0F0F0F0F0F0ULL,                               /*   8 */
+    0x0F0F0F0F0F0F0F0FULL,
+    0xF83E0F83E0F83E0FULL,
+    0x07C1F07C1F07C1F0ULL,
+    0xFC0FC0FC0FC0FC0FULL,
+    0x03F03F03F03F03F0ULL,
+    0xFE03F80FE03F80FEULL,
+    0x01FC07F01FC07F01ULL,
+    0xFF00FF00FF00FF00ULL,                               /*  16 */
+    0x00FF00FF00FF00FFULL,
+    0xFF803FE00FF803FEULL,
+    0x007FC01FF007FC01ULL,
+    0xFFC00FFC00FFC00FULL,
+    0x003FF003FF003FF0ULL,
+    0xFFE003FF800FFE00ULL,
+    0x001FFC007FF001FFULL,
+    0xFFF000FFF000FFF0ULL,                               /*  24 */
+    0x000FFF000FFF000FULL,
+    0xFFF8003FFE000FFFULL,
+    0x0007FFC001FFF000ULL,
+    0xFFFC000FFFC000FFULL,
+    0x0003FFF0003FFF00ULL,
+    0xFFFE0003FFF8000FULL,
+    0x0001FFFC0007FFF0ULL,
+    0xFFFF0000FFFF0000ULL,                               /*  32 */
+    0x0000FFFF0000FFFFULL,
+    0xFFFF80003FFFE000ULL,
+    0x00007FFFC0001FFFULL,
+    0xFFFFC0000FFFFC00ULL,
+    0x00003FFFF00003FFULL,
+    0xFFFFE00003FFFF80ULL,
+    0x00001FFFFC00007FULL,
+    0xFFFFF00000FFFFF0ULL,                               /*  40 */
+    0x00000FFFFF00000FULL,
+    0xFFFFF800003FFFFEULL,
+    0x000007FFFFC00001ULL,
+    0xFFFFFC00000FFFFFULL,
+    0x000003FFFFF00000ULL,
+    0xFFFFFE000003FFFFULL,
+    0x000001FFFFFC0000ULL,
+    0xFFFFFF000000FFFFULL,                               /*  48 */
+    0x000000FFFFFF0000ULL,
+    0xFFFFFF8000003FFFULL,
+    0x0000007FFFFFC000ULL,
+    0xFFFFFFC000000FFFULL,
+    0x0000003FFFFFF000ULL,
+    0xFFFFFFE0000003FFULL,
+    0x0000001FFFFFFC00ULL,
+    0xFFFFFFF0000000FFULL,                               /*  56 */
+    0x0000000FFFFFFF00ULL,
+    0xFFFFFFF80000003FULL,
+    0x00000007FFFFFFC0ULL,
+    0xFFFFFFFC0000000FULL,
+    0x00000003FFFFFFF0ULL,
+    0xFFFFFFFE00000003ULL,
+    0x00000001FFFFFFFCULL,
+};
+
+static const uint64_t b64_pattern_se[PATTERN_INPUTS_64_COUNT] = {
+    0xFFFFFFFFFFFFFFFFULL,                               /*   0 */
+    0x0000000000000000ULL,
+    0xFFFFFFFFAAAAAAAAULL,
+    0x0000000055555555ULL,
+    0xFFFFFFFFCCCCCCCCULL,
+    0x0000000033333333ULL,
+    0xFFFFFFFFE38E38E3ULL,
+    0x000000001C71C71CULL,
+    0xFFFFFFFFF0F0F0F0ULL,                               /*   8 */
+    0x000000000F0F0F0FULL,
+    0xFFFFFFFFF83E0F83ULL,
+    0x0000000007C1F07CULL,
+    0xFFFFFFFFFC0FC0FCULL,
+    0x0000000003F03F03ULL,
+    0xFFFFFFFFFE03F80FULL,
+    0x0000000001FC07F0ULL,
+    0xFFFFFFFFFF00FF00ULL,                               /*  16 */
+    0x0000000000FF00FFULL,
+    0xFFFFFFFFFF803FE0ULL,
+    0x00000000007FC01FULL,
+    0xFFFFFFFFFFC00FFCULL,
+    0x00000000003FF003ULL,
+    0xFFFFFFFFFFE003FFULL,
+    0x00000000001FFC00ULL,
+    0xFFFFFFFFFFF000FFULL,                               /*  24 */
+    0x00000000000FFF00ULL,
+    0xFFFFFFFFFFF8003FULL,
+    0x000000000007FFC0ULL,
+    0xFFFFFFFFFFFC000FULL,
+    0x000000000003FFF0ULL,
+    0xFFFFFFFFFFFE0003ULL,
+    0x000000000001FFFCULL,
+    0xFFFFFFFFFFFF0000ULL,                               /*  32 */
+    0x000000000000FFFFULL,
+    0xFFFFFFFFFFFF8000ULL,
+    0x0000000000007FFFULL,
+    0xFFFFFFFFFFFFC000ULL,
+    0x0000000000003FFFULL,
+    0xFFFFFFFFFFFFE000ULL,
+    0x0000000000001FFFULL,
+    0xFFFFFFFFFFFFF000ULL,                               /*  40 */
+    0x0000000000000FFFULL,
+    0xFFFFFFFFFFFFF800ULL,
+    0x00000000000007FFULL,
+    0xFFFFFFFFFFFFFC00ULL,
+    0x00000000000003FFULL,
+    0xFFFFFFFFFFFFFE00ULL,
+    0x00000000000001FFULL,
+    0xFFFFFFFFFFFFFF00ULL,                               /*  48 */
+    0x00000000000000FFULL,
+    0xFFFFFFFFFFFFFF80ULL,
+    0x000000000000007FULL,
+    0xFFFFFFFFFFFFFFC0ULL,
+    0x000000000000003FULL,
+    0xFFFFFFFFFFFFFFE0ULL,
+    0x000000000000001FULL,
+    0xFFFFFFFFFFFFFFF0ULL,                               /*  56 */
+    0x000000000000000FULL,
+    0xFFFFFFFFFFFFFFF8ULL,
+    0x0000000000000007ULL,
+    0xFFFFFFFFFFFFFFFCULL,
+    0x0000000000000003ULL,
+    0xFFFFFFFFFFFFFFFEULL,
+    0x0000000000000001ULL,
+};
+
+
+#define RANDOM_INPUTS_64_COUNT           16
+#define RANDOM_INPUTS_64_SHORT_COUNT      4
+
+static const uint64_t b64_random[RANDOM_INPUTS_64_COUNT] = {
+    0x886AE6CC28625540ULL,                               /*   0 */
+    0xFBBE00634D93C708ULL,
+    0xAC5AAEAAB9CF8B80ULL,
+    0x704F164D5E31E24EULL,
+    0xB9926B7C7DAF4258ULL,
+    0xD027BE89FF0A2EF9ULL,
+    0xB83B580665CABC4AULL,
+    0xFC8F23F09AA6B782ULL,
+    0x201E09CD56AEE649ULL,                               /*   8 */
+    0xA57CD91365D9E5D7ULL,
+    0xA2E8F6F5C9CBC61BULL,
+    0xA89CF2F131A864AEULL,
+    0xE61438E9A652EA0AULL,
+    0x944A35FD192361A8ULL,
+    0x4630426322BEF79CULL,
+    0x8B5AA7A2F259DEADULL,
+};
+
+static const uint64_t b64_random_se[RANDOM_INPUTS_64_COUNT] = {
+    0xFFFFFFFF886AE6CCULL,                               /*   0 */
+    0xFFFFFFFFFBBE0063ULL,
+    0xFFFFFFFFAC5AAEAAULL,
+    0x00000000704F164DULL,
+    0xFFFFFFFFB9926B7CULL,
+    0xFFFFFFFFD027BE89ULL,
+    0xFFFFFFFFB83B5806ULL,
+    0xFFFFFFFFFC8F23F0ULL,
+    0x00000000201E09CDULL,                               /*   8 */
+    0xFFFFFFFFA57CD913ULL,
+    0xFFFFFFFFA2E8F6F5ULL,
+    0xFFFFFFFFA89CF2F1ULL,
+    0xFFFFFFFFE61438E9ULL,
+    0xFFFFFFFF944A35FDULL,
+    0x0000000046304263ULL,
+    0xFFFFFFFF8B5AA7A2ULL,
+};
+
+
+#endif
diff --git a/tests/tcg/mips/include/test_utils.h b/tests/tcg/mips/include/test_utils.h
index 82f4b5b1ef..9672903eb5 100644
--- a/tests/tcg/mips/include/test_utils.h
+++ b/tests/tcg/mips/include/test_utils.h
@@ -27,14 +27,14 @@
 #include <inttypes.h>
 #include <string.h>
 
-#define PRINT_RESULTS 1
+#define PRINT_RESULTS 0
 
 
-static inline int32_t check_results(char *instruction_name,
-                                    uint32_t test_count,
-                                    double elapsed_time,
-                                    uint64_t *b128_result,
-                                    uint64_t *b128_expect)
+static inline int32_t check_results(const char *instruction_name,
+                                    const uint32_t test_count,
+                                    const double elapsed_time,
+                                    const uint64_t *b128_result,
+                                    const uint64_t *b128_expect)
 {
 #if PRINT_RESULTS
     uint32_t ii;
@@ -58,7 +58,8 @@ static inline int32_t check_results(char *instruction_name,
 
     printf("%s:   ", instruction_name);
     for (i = 0; i < test_count; i++) {
-        if (b128_result[i] == b128_expect[i]) {
+        if ((b128_result[2 * i] == b128_expect[2 * i]) &&
+            (b128_result[2 * i + 1] == b128_expect[2 * i + 1])) {
             pass_count++;
         } else {
             fail_count++;
diff --git a/tests/tcg/mips/include/test_utils_32.h b/tests/tcg/mips/include/test_utils_32.h
new file mode 100644
index 0000000000..c33990c0c5
--- /dev/null
+++ b/tests/tcg/mips/include/test_utils_32.h
@@ -0,0 +1,78 @@
+/*
+ *  Header file for test utilities
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef TEST_UTILS_32_H
+#define TEST_UTILS_32_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <string.h>
+
+#define PRINT_RESULTS 0
+
+
+static inline int32_t check_results_32(const char *instruction_name,
+                                       const uint32_t test_count,
+                                       const double elapsed_time,
+                                       const uint32_t *b32_result,
+                                       const uint32_t *b32_expect)
+{
+#if PRINT_RESULTS
+    uint32_t ii;
+    printf("\n");
+    for (ii = 0; ii < test_count; ii++) {
+        uint64_t a;
+        memcpy(&a, (b32_result + ii), 8);
+        if (ii % 8 != 0) {
+            printf("        0x%08lxULL,\n", a);
+        } else {
+            printf("        0x%08lxULL,                   /* %3d  */\n",
+                   a, ii);
+        }
+    }
+    printf("\n");
+#endif
+    uint32_t i;
+    uint32_t pass_count = 0;
+    uint32_t fail_count = 0;
+
+    printf("%s:   ", instruction_name);
+    for (i = 0; i < test_count; i++) {
+        if (b32_result[i] == b32_expect[i]) {
+            pass_count++;
+        } else {
+            fail_count++;
+        }
+    }
+
+    printf("PASS: %3d   FAIL: %3d   elapsed time: %5.2f ms\n",
+           pass_count, fail_count, elapsed_time);
+
+    if (fail_count > 0) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+
+#endif
diff --git a/tests/tcg/mips/include/test_utils_64.h b/tests/tcg/mips/include/test_utils_64.h
new file mode 100644
index 0000000000..ee3828472c
--- /dev/null
+++ b/tests/tcg/mips/include/test_utils_64.h
@@ -0,0 +1,78 @@
+/*
+ *  Header file for test utilities
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef TEST_UTILS_64_H
+#define TEST_UTILS_64_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <string.h>
+
+#define PRINT_RESULTS 0
+
+
+static inline int32_t check_results_64(const char *instruction_name,
+                                       const uint32_t test_count,
+                                       const double elapsed_time,
+                                       const uint64_t *b64_result,
+                                       const uint64_t *b64_expect)
+{
+#if PRINT_RESULTS
+    uint32_t ii;
+    printf("\n");
+    for (ii = 0; ii < test_count; ii++) {
+        uint64_t a;
+        memcpy(&a, (b64_result + ii), 8);
+        if (ii % 8 != 0) {
+            printf("        0x%016llxULL,\n", a);
+        } else {
+            printf("        0x%016llxULL,                    /* %3d  */\n",
+                   a, ii);
+        }
+    }
+    printf("\n");
+#endif
+    uint32_t i;
+    uint32_t pass_count = 0;
+    uint32_t fail_count = 0;
+
+    printf("%s:   ", instruction_name);
+    for (i = 0; i < test_count; i++) {
+        if (b64_result[i] == b64_expect[i]) {
+            pass_count++;
+        } else {
+            fail_count++;
+        }
+    }
+
+    printf("PASS: %3d   FAIL: %3d   elapsed time: %5.2f ms\n",
+           pass_count, fail_count, elapsed_time);
+
+    if (fail_count > 0) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+
+#endif
diff --git a/tests/tcg/mips/include/wrappers_mips64r6.h b/tests/tcg/mips/include/wrappers_mips64r6.h
new file mode 100644
index 0000000000..d1e5edb632
--- /dev/null
+++ b/tests/tcg/mips/include/wrappers_mips64r6.h
@@ -0,0 +1,83 @@
+/*
+ *  Header file for wrappers around MIPS64R6 instructions assembler
+ *  invocations
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef WRAPPERS_MIPS64R6_H
+#define WRAPPERS_MIPS64R6_H
+
+
+#define DO_MIPS64R6__RD__RS(suffix, mnemonic)                          \
+static inline void do_mips64r6_##suffix(const void *input,             \
+                                        void *output)                  \
+{                                                                      \
+   __asm__ volatile (                                                  \
+      "ld $t1, 0(%0)\n\t"                                              \
+      #mnemonic " $t0, $t1\n\t"                                        \
+      "sd $t0, 0(%1)\n\t"                                              \
+      :                                                                \
+      : "r" (input), "r" (output)                                      \
+      : "t0", "t1", "memory"                                           \
+   );                                                                  \
+}
+
+DO_MIPS64R6__RD__RS(CLO, clo)
+DO_MIPS64R6__RD__RS(CLZ, clz)
+DO_MIPS64R6__RD__RS(DCLO, dclo)
+DO_MIPS64R6__RD__RS(DCLZ, dclz)
+
+DO_MIPS64R6__RD__RS(BITSWAP, bitswap)
+DO_MIPS64R6__RD__RS(DBITSWAP, dbitswap)
+
+
+#define DO_MIPS64R6__RD__RS_RT(suffix, mnemonic)                       \
+static inline void do_mips64r6_##suffix(const void *input1,            \
+                                        const void *input2,            \
+                                        void *output)                  \
+{                                                                      \
+   __asm__ volatile (                                                  \
+      "ld $t1, 0(%0)\n\t"                                              \
+      "ld $t2, 0(%1)\n\t"                                              \
+      #mnemonic " $t0, $t1, $t2\n\t"                                   \
+      "sd $t0, 0(%2)\n\t"                                              \
+      :                                                                \
+      : "r" (input1), "r" (input2), "r" (output)                       \
+      : "t0", "t1", "memory"                                           \
+   );                                                                  \
+}
+
+DO_MIPS64R6__RD__RS_RT(SLLV, sllv)
+DO_MIPS64R6__RD__RS_RT(SRLV, srlv)
+DO_MIPS64R6__RD__RS_RT(SRAV, srav)
+DO_MIPS64R6__RD__RS_RT(DSLLV, dsllv)
+DO_MIPS64R6__RD__RS_RT(DSRLV, dsrlv)
+DO_MIPS64R6__RD__RS_RT(DSRAV, dsrav)
+
+DO_MIPS64R6__RD__RS_RT(MUL, mul)
+DO_MIPS64R6__RD__RS_RT(MUH, muh)
+DO_MIPS64R6__RD__RS_RT(MULU, mulu)
+DO_MIPS64R6__RD__RS_RT(MUHU, muhu)
+DO_MIPS64R6__RD__RS_RT(DMUL, dmul)
+DO_MIPS64R6__RD__RS_RT(DMUH, dmuh)
+DO_MIPS64R6__RD__RS_RT(DMULU, dmulu)
+DO_MIPS64R6__RD__RS_RT(DMUHU, dmuhu)
+
+
+#endif
diff --git a/tests/tcg/mips/include/wrappers_msa.h b/tests/tcg/mips/include/wrappers_msa.h
index 302f0ab54c..9cffd55591 100644
--- a/tests/tcg/mips/include/wrappers_msa.h
+++ b/tests/tcg/mips/include/wrappers_msa.h
@@ -38,6 +38,21 @@ static inline void do_msa_##suffix(void *input, void *output)          \
    );                                                                  \
 }
 
+#define DO_MSA__WD__WD(suffix, mnemonic)                               \
+static inline void do_msa_##suffix(void *input, void *output)          \
+{                                                                      \
+   __asm__ volatile (                                                  \
+      "move $t0, %0\n\t"                                               \
+      "ld.d $w11, 0($t0)\n\t"                                          \
+      #mnemonic " $w10, $w10\n\t"                                      \
+      "move $t0, %1\n\t"                                               \
+      "st.d $w10, 0($t0)\n\t"                                          \
+      :                                                                \
+      : "r" (input), "r" (output)                                      \
+      : "t0", "memory"                                                 \
+   );                                                                  \
+}
+
 DO_MSA__WD__WS(NLOC_B, nloc.b)
 DO_MSA__WD__WS(NLOC_H, nloc.h)
 DO_MSA__WD__WS(NLOC_W, nloc.w)
@@ -72,6 +87,42 @@ static inline void do_msa_##suffix(void *input1, void *input2,         \
    );                                                                  \
 }
 
+#define DO_MSA__WD__WD_WT(suffix, mnemonic)                            \
+static inline void do_msa_##suffix(void *input1, void *input2,         \
+                                   void *output)                       \
+{                                                                      \
+   __asm__ volatile (                                                  \
+      "move $t0, %0\n\t"                                               \
+      "ld.d $w11, 0($t0)\n\t"                                          \
+      "move $t0, %1\n\t"                                               \
+      "ld.d $w12, 0($t0)\n\t"                                          \
+      #mnemonic " $w10, $w10, $w12\n\t"                                \
+      "move $t0, %2\n\t"                                               \
+      "st.d $w10, 0($t0)\n\t"                                          \
+      :                                                                \
+      : "r" (input1), "r" (input2), "r" (output)                       \
+      : "t0", "memory"                                                 \
+   );                                                                  \
+}
+
+#define DO_MSA__WD__WS_WD(suffix, mnemonic)                            \
+static inline void do_msa_##suffix(void *input1, void *input2,         \
+                                   void *output)                       \
+{                                                                      \
+   __asm__ volatile (                                                  \
+      "move $t0, %0\n\t"                                               \
+      "ld.d $w11, 0($t0)\n\t"                                          \
+      "move $t0, %1\n\t"                                               \
+      "ld.d $w12, 0($t0)\n\t"                                          \
+      #mnemonic " $w10, $w11, $w10\n\t"                                \
+      "move $t0, %2\n\t"                                               \
+      "st.d $w10, 0($t0)\n\t"                                          \
+      :                                                                \
+      : "r" (input1), "r" (input2), "r" (output)                       \
+      : "t0", "memory"                                                 \
+   );                                                                  \
+}
+
 DO_MSA__WD__WS_WT(ILVEV_B, ilvev.b)
 DO_MSA__WD__WS_WT(ILVEV_H, ilvev.h)
 DO_MSA__WD__WS_WT(ILVEV_W, ilvev.w)
@@ -152,5 +203,75 @@ DO_MSA__WD__WS_WT(MIN_U_H, min_u.h)
 DO_MSA__WD__WS_WT(MIN_U_W, min_u.w)
 DO_MSA__WD__WS_WT(MIN_U_D, min_u.d)
 
+DO_MSA__WD__WS_WT(BCLR_B, bclr.b)
+DO_MSA__WD__WS_WT(BCLR_H, bclr.h)
+DO_MSA__WD__WS_WT(BCLR_W, bclr.w)
+DO_MSA__WD__WS_WT(BCLR_D, bclr.d)
+
+DO_MSA__WD__WS_WT(BSET_B, bset.b)
+DO_MSA__WD__WS_WT(BSET_H, bset.h)
+DO_MSA__WD__WS_WT(BSET_W, bset.w)
+DO_MSA__WD__WS_WT(BSET_D, bset.d)
+
+DO_MSA__WD__WS_WT(BNEG_B, bneg.b)
+DO_MSA__WD__WS_WT(BNEG_H, bneg.h)
+DO_MSA__WD__WS_WT(BNEG_W, bneg.w)
+DO_MSA__WD__WS_WT(BNEG_D, bneg.d)
+
+DO_MSA__WD__WS_WT(PCKEV_B, pckev.b)
+DO_MSA__WD__WS_WT(PCKEV_H, pckev.h)
+DO_MSA__WD__WS_WT(PCKEV_W, pckev.w)
+DO_MSA__WD__WS_WT(PCKEV_D, pckev.d)
+
+DO_MSA__WD__WS_WT(PCKOD_B, pckod.b)
+DO_MSA__WD__WS_WT(PCKOD_H, pckod.h)
+DO_MSA__WD__WS_WT(PCKOD_W, pckod.w)
+DO_MSA__WD__WS_WT(PCKOD_D, pckod.d)
+
+DO_MSA__WD__WS_WT(VSHF_B, vshf.b)
+DO_MSA__WD__WS_WT(VSHF_H, vshf.h)
+DO_MSA__WD__WS_WT(VSHF_W, vshf.w)
+DO_MSA__WD__WS_WT(VSHF_D, vshf.d)
+
+DO_MSA__WD__WS_WT(SLL_B, sll.b)
+DO_MSA__WD__WS_WT(SLL_H, sll.h)
+DO_MSA__WD__WS_WT(SLL_W, sll.w)
+DO_MSA__WD__WS_WT(SLL_D, sll.d)
+
+DO_MSA__WD__WS_WT(SRA_B, sra.b)
+DO_MSA__WD__WS_WT(SRA_H, sra.h)
+DO_MSA__WD__WS_WT(SRA_W, sra.w)
+DO_MSA__WD__WS_WT(SRA_D, sra.d)
+
+DO_MSA__WD__WS_WT(SRAR_B, srar.b)
+DO_MSA__WD__WS_WT(SRAR_H, srar.h)
+DO_MSA__WD__WS_WT(SRAR_W, srar.w)
+DO_MSA__WD__WS_WT(SRAR_D, srar.d)
+
+DO_MSA__WD__WS_WT(SRL_B, srl.b)
+DO_MSA__WD__WS_WT(SRL_H, srl.h)
+DO_MSA__WD__WS_WT(SRL_W, srl.w)
+DO_MSA__WD__WS_WT(SRL_D, srl.d)
+
+DO_MSA__WD__WS_WT(SRLR_B, srlr.b)
+DO_MSA__WD__WS_WT(SRLR_H, srlr.h)
+DO_MSA__WD__WS_WT(SRLR_W, srlr.w)
+DO_MSA__WD__WS_WT(SRLR_D, srlr.d)
+
+DO_MSA__WD__WS_WT(BMNZ_V, bmnz.v)
+DO_MSA__WD__WS_WT(BMZ_V, bmz.v)
+
+DO_MSA__WD__WS_WT(FMAX_W, fmax.w)
+DO_MSA__WD__WS_WT(FMAX_D, fmax.d)
+
+DO_MSA__WD__WS_WT(FMAX_A_W, fmax_a.w)
+DO_MSA__WD__WS_WT(FMAX_A_D, fmax_a.d)
+
+DO_MSA__WD__WS_WT(FMIN_W, fmin.w)
+DO_MSA__WD__WS_WT(FMIN_D, fmin.d)
+
+DO_MSA__WD__WS_WT(FMIN_A_W, fmin_a.w)
+DO_MSA__WD__WS_WT(FMIN_A_D, fmin_a.d)
+
 
 #endif