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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
| commit | a09863610aefe17390612b7d78d3fba20e43b53e (patch) | |
| tree | dcf39f4859c516dc5447ad3d0f1dc8f72af03ae3 /tests | |
| parent | 1d60bb4b14601e38ed17384277aa4c30c57925d3 (diff) | |
| parent | 79d54c9eac04c554e3c081589542f801ace71797 (diff) | |
| download | focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.tar.gz focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.zip | |
Merge tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix sve2 ldnt1 and stnt1 * Fix pauth_check_trap vs SEL2 * Fix handling of LPAE block descriptors * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() * nsis installer: List emulators in alphabetical order * nsis installer: Suppress "ANSI targets are deprecated" warning * nsis installer: Fix mouse-over descriptions for emulators * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset * Improve M-profile vector table access logging * Xilinx ZynqMP: model CRF and APU control * Fix compile issues on modern Solaris # gpg: Signature made Fri 18 Mar 2022 13:18:20 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) util/osdep: Remove some early cruft hw/i386/acpi-build: Avoid 'sun' identifier util/osdep: Avoid madvise proto on modern Solaris hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control hw/misc: Add a model of the Xilinx ZynqMP APU Control hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF hw/misc: Add a model of the Xilinx ZynqMP CRF target/arm: Make rvbar settable after realize hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area target/arm: Log fault address for M-profile faults target/arm: Log M-profile vector table accesses hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG nsis installer: Fix mouse-over descriptions for emulators nsis installer: Suppress "ANSI targets are deprecated" warning nsis installer: List emulators in alphabetical order hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size target/arm: Fix handling of LPAE block descriptors target/arm: Fix pauth_check_trap vs SEL2 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/tcg/aarch64/Makefile.target | 4 | ||||
| -rw-r--r-- | tests/tcg/aarch64/test-826.c | 50 | ||||
| -rwxr-xr-x | tests/tcg/configure.sh | 4 |
3 files changed, 58 insertions, 0 deletions
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index ac07acde66..f7121cb4d8 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -86,7 +86,11 @@ run-gdbstub-sve-ioctls: sve-ioctls EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls endif +endif +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),) +AARCH64_TESTS += test-826 +test-826: CFLAGS+=-march=armv8.1-a+sve2 endif TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c new file mode 100644 index 0000000000..f59740a8c5 --- /dev/null +++ b/tests/tcg/aarch64/test-826.c @@ -0,0 +1,50 @@ +#include <sys/mman.h> +#include <unistd.h> +#include <signal.h> +#include <stdlib.h> +#include <stdio.h> +#include <assert.h> + +static void *expected; + +void sigsegv(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc = vuc; + + assert(info->si_addr == expected); + uc->uc_mcontext.pc += 4; +} + +int main() +{ + struct sigaction sa = { + .sa_sigaction = sigsegv, + .sa_flags = SA_SIGINFO + }; + + void *page; + long ofs; + + if (sigaction(SIGSEGV, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0); + if (page == MAP_FAILED) { + perror("mmap"); + return EXIT_FAILURE; + } + + ofs = 0x124; + expected = page + ofs; + + asm("ptrue p0.d, vl1\n\t" + "dup z0.d, %0\n\t" + "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t" + "dup z1.d, %1\n\t" + "ldnt1h {z0.d}, p0/z, [z1.d, %0]" + : : "r"(page), "r"(ofs) : "v0", "v1"); + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index ed4b5ccb1f..84f928f7f8 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -300,6 +300,10 @@ for target in $target_list; do echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak fi if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=armv8.1-a+sve2 -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak + fi + if do_compiler "$target_compiler" $target_compiler_cflags \ -march=armv8.3-a -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak fi |