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| author | SillyZ <1357816113@qq.com> | 2025-09-16 16:10:09 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2025-10-05 09:46:06 +0300 |
| commit | d56a30a7bba66de1b796af775928f77da25ca89b (patch) | |
| tree | 51c8777ebfb4a112f05b9a6e954b9c5c2e8990ab /tests | |
| parent | c187a67c9dcdece58138f4df5ca4dd846934eddc (diff) | |
| download | focaccia-qemu-d56a30a7bba66de1b796af775928f77da25ca89b.tar.gz focaccia-qemu-d56a30a7bba66de1b796af775928f77da25ca89b.zip | |
hw/net/can: Remove redundant status bit setting in can_sja1000
In PeliCAN mode reception, the RBS (Receive Buffer Status) bit is set twice at line 842 and 845 with identical operations: s->status_pel |= 0x01; s->status_pel |= (1 << 0); Between these two operations, only interrupt_pel is modified and status_pel bit 4 is cleared, neither affecting bit 0. The second operation is redundant. This cleanup aligns PeliCAN mode with BasicCAN mode, which correctly sets this bit only once (line 883). Signed-off-by: SillyZ <1357816113@qq.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions