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| author | Jingqi Liu <jingqi.liu@intel.com> | 2018-05-04 11:57:33 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-05-15 11:33:33 -0300 |
| commit | 0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff (patch) | |
| tree | 547888449f60dd37964bd7d33987fb8cd2365cec /util/async.c | |
| parent | a18495159a35e9c5973d9aa0f612a97318bf684d (diff) | |
| download | focaccia-qemu-0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff.tar.gz focaccia-qemu-0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff.zip | |
x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature
The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other cores in the same coherence domain,
especially if the line was written by the core that demotes the line.
Intel Snow Ridge has added new cpu feature, CLDEMOTE.
The new cpu feature needs to be exposed to guest VM.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'util/async.c')
0 files changed, 0 insertions, 0 deletions