Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging

tcg: Merge two sequential labels
accel/tcg: Retain prot flags from tlb_fill
accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup
accel/tcg: Honor TLB_WATCHPOINTS in atomic_mmu_lookup
target/sparc: Use tlb_set_page_full
include/qemu/cpuid: Introduce xgetbv_low
tcg/i386: Mark Win64 call-saved vector regs as reserved
tcg: Decode the operand to INDEX_op_mb in dumps

Portion of the target/ patchset which eliminates use of tcg_temp_free*
Portion of the target/ patchset which eliminates use of tcg_const*

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* tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu: (84 commits)
  target/xtensa: Avoid tcg_const_i32
  target/xtensa: Split constant in bit shift
  target/xtensa: Use tcg_gen_subfi_i32 in translate_sll
  target/xtensa: Avoid tcg_const_i32 in translate_l32r
  target/xtensa: Tidy translate_clamps
  target/xtensa: Tidy translate_bb
  target/sparc: Avoid tcg_const_{tl,i32}
  target/s390x: Split out gen_ri2
  target/riscv: Avoid tcg_const_*
  target/microblaze: Avoid tcg_const_* throughout
  target/i386: Simplify POPF
  target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op
  target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred
  target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign
  target/hexagon/idef-parser: Use gen_tmp for LPCFG
  target/hexagon: Use tcg_constant_* for gen_constant_from_imm
  docs/devel/tcg-ops: Drop recommendation to free temps
  tracing: remove transform.py
  include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start
  target/tricore: Drop tcg_temp_free
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 1 insertions, 2 deletions

diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index 1790ded7d4..1886bc5ba4 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -258,8 +258,7 @@ static void __attribute__((constructor)) init_cpuid_cache(void)
 
         /* We must check that AVX is not just available, but usable.  */
         if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >= 7) {
-            int bv;
-            __asm("xgetbv" : "=a"(bv), "=d"(d) : "c"(0));
+            unsigned bv = xgetbv_low(0);
             __cpuid_count(7, 0, a, b, c, d);
             if ((bv & 0x6) == 0x6 && (b & bit_AVX2)) {
                 cache |= CACHE_AVX2;