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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-08 07:17:37 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:25:27 -0700 |
| commit | 621c1006d2d82da9f266f21ad8e887c38769a11b (patch) | |
| tree | aa8f0f30f8d1082f9f2a1255568850ead7f49285 /util/coroutine-sigaltstack.c | |
| parent | 8a88b9f54f5fb2acecf73760903b1f58fb40d0cd (diff) | |
| download | focaccia-qemu-621c1006d2d82da9f266f21ad8e887c38769a11b.tar.gz focaccia-qemu-621c1006d2d82da9f266f21ad8e887c38769a11b.zip | |
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
At present the GPIO output IRQs are triggered each time any GPIO register is written. However this is not correct. We should only trigger the output IRQ when the pin is configured as output enable. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'util/coroutine-sigaltstack.c')
0 files changed, 0 insertions, 0 deletions