summary refs log tree commit diff stats
path: root/util/mmap-alloc.c
diff options
context:
space:
mode:
authorSuraj Jitindar Singh <sjitindarsingh@gmail.com>2017-03-01 18:12:54 +1100
committerDavid Gibson <david@gibson.dropbear.id.au>2017-03-03 11:30:59 +1100
commit07a68f990785a8574c78a36b21cf5165e46f1113 (patch)
treeec2a208ab06040a3b57845b492a1bb4eca3a1f98 /util/mmap-alloc.c
parent347a5c73bafd1b5872c9d3192a4d08f8aa1d5f5a (diff)
downloadfocaccia-qemu-07a68f990785a8574c78a36b21cf5165e46f1113.tar.gz
focaccia-qemu-07a68f990785a8574c78a36b21cf5165e46f1113.zip
target/ppc: Move no-execute and guarded page checking into new function
A pte entry has bit fields which can be used to make a page no-execute or
guarded, if either of these bits are set then an instruction access to this
page will fail. Currently these bits are checked with the pp_prot function
however the ISA specifies that the access authority controlled by the
key-pp value pair should only be checked on an instruction access after
the no-execute and guard bits have already been verified to permit the
access.

Move the no-execute and guard bit checking into a new separate function.
Note that we can remove the check for the no-execute bit in the slb entry
since this check was already performed above when we obtained the slb
entry.

In the event that the no-execute or guard bits are set, an ISI should be
generated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a
define for this for clarity.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[dwg: Move constants to cpu.h since they're not MMUv3 specific]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'util/mmap-alloc.c')
0 files changed, 0 insertions, 0 deletions