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| author | Zenghui Yu <yuzenghui@huawei.com> | 2021-04-02 16:47:31 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-12 11:06:24 +0100 |
| commit | 0c38f607836af40921ea2b58676b7c4a9fe33bef (patch) | |
| tree | 6aba5d71dedf8f3ccdc7365eaf9a9697a98f340a /util/qemu-timer.c | |
| parent | 555249a59e9cdd6b58da103aba5cf3a2d45c899f (diff) | |
| download | focaccia-qemu-0c38f607836af40921ea2b58676b7c4a9fe33bef.tar.gz focaccia-qemu-0c38f607836af40921ea2b58676b7c4a9fe33bef.zip | |
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'util/qemu-timer.c')
0 files changed, 0 insertions, 0 deletions