diff options
| -rw-r--r-- | hw/ppc/spapr.c | 2 | ||||
| -rw-r--r-- | include/hw/ppc/spapr_ovec.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 06a008b43c..f680f28a15 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -937,7 +937,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); char val[2 * 4] = { - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ + 23, 0x00, /* Xive mode, filled in below. */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 26, 0x40, /* Radix options: GTSE == yes. */ diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 9edfa5ff75..bf25e5d954 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) #define OV5_HPT_RESIZE OV_BIT(6, 7) -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) +#define OV5_XIVE_BOTH OV_BIT(23, 0) +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ /* ISA 3.00 MMU features: */ #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */ |