diff options
| -rw-r--r-- | target-tricore/op_helper.c | 3 | ||||
| -rw-r--r-- | target-tricore/translate.c | 6 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 2 |
3 files changed, 6 insertions, 5 deletions
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 9907e07e22..9919b5b17b 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -2458,6 +2458,7 @@ void helper_rfe(CPUTriCoreState *env) if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) { /* raise MNG trap */ } + env->PC = env->gpr_a[11] & ~0x1; /* ICR.IE = PCXI.PIE; */ env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15); /* ICR.CCPN = PCXI.PCPN; */ @@ -2581,7 +2582,7 @@ void helper_rslcx(CPUTriCoreState *env) ((env->PCXI & MASK_PCXI_PCXO) << 6); /* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */ - restore_context_upper(env, ea, &new_PCXI, &env->gpr_a[11]); + restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI); /* M(EA, word) = FCX; */ cpu_stl_data(env, ea, env->FCX); /* M(EA, word) = FCX; */ diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 54a48cd694..663b2a0796 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; case OPCM_32_BRR_LOOP: if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { - gen_loop(ctx, r1, offset * 2); + gen_loop(ctx, r2, offset * 2); } else { /* OPC2_32_BRR_LOOPU */ gen_goto_tb(ctx, 0, ctx->pc + offset * 2); @@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1) tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); break; case OPC1_16_SLR_LD_W: - tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); + tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); break; case OPC1_16_SLR_LD_W_POSTINC: - tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); + tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); break; } diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index d3a9bc158b..2291f75fd9 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -107,7 +107,7 @@ /* BO Format */ #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \ (MASK_BITS_SHIFT(op, 28, 31) << 6)) -#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \ +#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT(op, 16, 21) + \ (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6)) #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27) #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15) |