diff options
| -rw-r--r-- | hw/ppc440_bamboo.c | 143 |
1 files changed, 60 insertions, 83 deletions
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index d00bddace5..f86b16838a 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -27,6 +27,7 @@ #include "ppc.h" #include "ppc405.h" #include "sysemu.h" +#include "sysbus.h" #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" @@ -50,87 +51,6 @@ static const unsigned int ppc440ep_sdram_bank_sizes[] = { static target_phys_addr_t entry; -static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], - target_phys_addr_t config_space, - target_phys_addr_t int_ack, - target_phys_addr_t special_cycle, - target_phys_addr_t registers) -{ - return NULL; -} - -CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size, - PCIBus **pcip, const unsigned int pci_irq_nrs[4], - int do_init, const char *cpu_model) -{ - MemoryRegion *ram_memories - = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); - target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; - target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; - CPUState *env; - qemu_irq *pic; - qemu_irq *irqs; - qemu_irq *pci_irqs; - - if (cpu_model == NULL) { - cpu_model = "440EP"; - } - env = cpu_init(cpu_model); - if (!env) { - fprintf(stderr, "Unable to initialize CPU!\n"); - exit(1); - } - - ppc_booke_timers_init(env, 400000000, 0); - ppc_dcr_init(env, NULL, NULL); - - /* interrupt controller */ - irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); - - /* SDRAM controller */ - memset(ram_bases, 0, sizeof(ram_bases)); - memset(ram_sizes, 0, sizeof(ram_sizes)); - *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, - ram_memories, - ram_bases, ram_sizes, - ppc440ep_sdram_bank_sizes); - /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes, do_init); - - /* PCI */ - pci_irqs = g_malloc(sizeof(qemu_irq) * 4); - pci_irqs[0] = pic[pci_irq_nrs[0]]; - pci_irqs[1] = pic[pci_irq_nrs[1]]; - pci_irqs[2] = pic[pci_irq_nrs[2]]; - pci_irqs[3] = pic[pci_irq_nrs[3]]; - *pcip = ppc4xx_pci_init(env, pci_irqs, - PPC440EP_PCI_CONFIG, - PPC440EP_PCI_INTACK, - PPC440EP_PCI_SPECIAL, - PPC440EP_PCI_REGS); - if (!*pcip) - printf("couldn't create PCI controller!\n"); - - isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); - - if (serial_hds[0] != NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], - DEVICE_BIG_ENDIAN); - } - if (serial_hds[1] != NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], - DEVICE_BIG_ENDIAN); - } - - return env; -} - static int bamboo_load_device_tree(target_phys_addr_t addr, uint32_t ramsize, target_phys_addr_t initrd_base, @@ -245,19 +165,76 @@ static void bamboo_init(ram_addr_t ram_size, { unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *ram_memories + = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); + target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; + target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; + qemu_irq *pic; + qemu_irq *irqs; PCIBus *pcibus; CPUState *env; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t loadaddr = 0; target_long initrd_size = 0; + DeviceState *dev; int success; int i; /* Setup CPU. */ - env = ppc440ep_init(address_space_mem, &ram_size, &pcibus, - pci_irq_nrs, 1, cpu_model); + if (cpu_model == NULL) { + cpu_model = "440EP"; + } + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to initialize CPU!\n"); + exit(1); + } + qemu_register_reset(main_cpu_reset, env); + ppc_booke_timers_init(env, 400000000, 0); + ppc_dcr_init(env, NULL, NULL); + + /* interrupt controller */ + irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); + irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; + irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; + pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); + + /* SDRAM controller */ + memset(ram_bases, 0, sizeof(ram_bases)); + memset(ram_sizes, 0, sizeof(ram_sizes)); + ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, + ram_memories, + ram_bases, ram_sizes, + ppc440ep_sdram_bank_sizes); + /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ + ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, + ram_bases, ram_sizes, 1); + + /* PCI */ + dev = sysbus_create_varargs("ppc4xx-pcihost", PPC440EP_PCI_CONFIG, + pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], + pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], + NULL); + pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); + if (!pcibus) { + fprintf(stderr, "couldn't create PCI controller!\n"); + exit(1); + } + + isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); + + if (serial_hds[0] != NULL) { + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + DEVICE_BIG_ENDIAN); + } + if (serial_hds[1] != NULL) { + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + DEVICE_BIG_ENDIAN); + } if (pcibus) { /* Register network interfaces. */ |