diff options
| -rw-r--r-- | hw/core/machine.c | 1 | ||||
| -rw-r--r-- | hw/pci-bridge/pcie_root_port.c | 3 | ||||
| -rw-r--r-- | include/hw/pci/pcie_port.h | 2 |
3 files changed, 5 insertions, 1 deletions
diff --git a/hw/core/machine.c b/hw/core/machine.c index c4a2ab2282..28a475ad97 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -52,6 +52,7 @@ GlobalProperty hw_compat_3_1[] = { { "virtio-blk-device", "discard", "false" }, { "virtio-blk-device", "write-zeroes", "false" }, { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, + { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ }; const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 09019ca05d..1d8a778709 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -111,7 +111,7 @@ static void rp_realize(PCIDevice *d, Error **errp) pcie_aer_root_init(d); rp_aer_vector_update(d); - if (rpc->acs_offset) { + if (rpc->acs_offset && !s->disable_acs) { pcie_acs_init(d, rpc->acs_offset); } return; @@ -145,6 +145,7 @@ static void rp_exit(PCIDevice *d) static Property rp_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), DEFINE_PROP_END_OF_LIST() }; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 09586f4641..7515430087 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -53,6 +53,8 @@ struct PCIESlot { PCIExpLinkSpeed speed; PCIExpLinkWidth width; + /* Disable ACS (really for a pcie_root_port) */ + bool disable_acs; QLIST_ENTRY(PCIESlot) next; }; |