diff options
| -rw-r--r-- | target-xtensa/cpu.c | 1 | ||||
| -rw-r--r-- | target-xtensa/cpu.h | 2 | ||||
| -rw-r--r-- | target-xtensa/helper.c | 21 | ||||
| -rw-r--r-- | target-xtensa/overlay_tool.h | 1 | ||||
| -rw-r--r-- | target-xtensa/translate.c | 1 |
5 files changed, 25 insertions, 1 deletions
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index c6aa45ee6f..035b07c1c5 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -48,6 +48,7 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index d240ab70d9..068ad69ee9 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -94,6 +94,7 @@ enum { XTENSA_OPTION_REGION_PROTECTION, XTENSA_OPTION_REGION_TRANSLATION, XTENSA_OPTION_MMU, + XTENSA_OPTION_CACHEATTR, /* Other */ XTENSA_OPTION_WINDOWED_REGISTER, @@ -129,6 +130,7 @@ enum { ITLBCFG = 91, DTLBCFG = 92, IBREAKENABLE = 96, + CACHEATTR = 98, ATOMCTL = 99, IBREAKA = 128, DBREAKA = 144, diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index ecd0182281..200fb43c28 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -438,6 +438,24 @@ static unsigned region_attr_to_access(uint32_t attr) return access[attr & 0xf]; } +/*! + * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, A.2.14 The Cache Attribute Register + */ +static unsigned cacheattr_attr_to_access(uint32_t attr) +{ + static const unsigned access[16] = { + [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, + [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, + [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, + [3] = PAGE_EXEC | PAGE_CACHE_WB, + [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, + }; + + return access[attr & 0xf]; +} + static bool is_access_granted(unsigned access, int is_write) { switch (is_write) { @@ -584,7 +602,8 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, } else { *paddr = vaddr; *page_size = TARGET_PAGE_SIZE; - *access = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS; + *access = cacheattr_attr_to_access( + env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27)); return 0; } } diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index 50bf5735e9..45205b8e67 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -91,6 +91,7 @@ XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ XTENSA_OPTION_REGION_TRANSLATION) | \ XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ + XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ /* Other, TODO */ \ XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG)) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index dc08de51ba..eb4812099e 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -99,6 +99,7 @@ static const char * const sregnames[256] = { [ITLBCFG] = "ITLBCFG", [DTLBCFG] = "DTLBCFG", [IBREAKENABLE] = "IBREAKENABLE", + [CACHEATTR] = "CACHEATTR", [ATOMCTL] = "ATOMCTL", [IBREAKA] = "IBREAKA0", [IBREAKA + 1] = "IBREAKA1", |