diff options
| -rw-r--r-- | hw/i386/pc.c | 4 | ||||
| -rw-r--r-- | target/i386/cpu.c | 7 | ||||
| -rw-r--r-- | target/i386/cpu.h | 7 |
3 files changed, 16 insertions, 2 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 432ab288a8..a6fa792368 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -81,7 +81,9 @@ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, -GlobalProperty pc_compat_10_0[] = {}; +GlobalProperty pc_compat_10_0[] = { + { TYPE_X86_CPU, "x-consistent-cache", "false" }, +}; const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); GlobalProperty pc_compat_9_2[] = {}; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3278d5de5a..1f27fcf3ee 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8935,7 +8935,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) /* Build legacy cache information */ env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; - env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; + if (!cpu->consistent_cache) { + env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; + } else { + env->cache_info_cpuid2.l2_cache = &legacy_l2_cache; + } env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; @@ -9461,6 +9465,7 @@ static const Property x86_cpu_properties[] = { * own cache information (see x86_cpu_load_def()). */ DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), + DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true), DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a580562b3d..a3ebd3e08c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2259,6 +2259,13 @@ struct ArchCPU { */ bool legacy_cache; + /* + * Compatibility bits for old machine types. + * If true, use the same cache model in CPUID leaf 0x2 + * and 0x4. + */ + bool consistent_cache; + /* Compatibility bits for old machine types. * If true decode the CPUID Function 0x8000001E_ECX to support multiple * nodes per processor |