diff options
| -rw-r--r-- | target-mips/cpu.h | 3 | ||||
| -rw-r--r-- | target-mips/exec.h | 1 | ||||
| -rw-r--r-- | target-mips/helper.c | 2 | ||||
| -rw-r--r-- | target-mips/mips-defs.h | 1 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 54 | ||||
| -rw-r--r-- | target-mips/translate.c | 1 |
6 files changed, 54 insertions, 8 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 330f9eb19c..3ade7bce64 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -94,7 +94,8 @@ struct CPUMIPSState { #endif #if defined(MIPS_USES_R4K_TLB) - tlb_t tlb[MIPS_TLB_NB]; + tlb_t tlb[MIPS_TLB_MAX]; + uint32_t tlb_in_use; #endif uint32_t CP0_index; uint32_t CP0_random; diff --git a/target-mips/exec.h b/target-mips/exec.h index 93014d6df8..a1cf685a16 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -115,5 +115,6 @@ uint32_t cpu_mips_get_count (CPUState *env); void cpu_mips_store_count (CPUState *env, uint32_t value); void cpu_mips_store_compare (CPUState *env, uint32_t value); void cpu_mips_clock_init (CPUState *env); +void cpu_mips_tlb_flush (CPUState *env, int flush_global); #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ diff --git a/target-mips/helper.c b/target-mips/helper.c index 9c8e4f68df..57318a5a34 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -46,7 +46,7 @@ static int map_address (CPUState *env, target_ulong *physical, int *prot, tlb_t *tlb; int i, n; - for (i = 0; i < MIPS_TLB_NB; i++) { + for (i = 0; i < env->tlb_in_use; i++) { tlb = &env->tlb[i]; /* Check ASID, virtual page number & size */ if ((tlb->G == 1 || tlb->ASID == ASID) && diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c6f9e9cbe2..63e64bbdce 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -22,6 +22,7 @@ /* Uses MIPS R4Kc TLB model */ #define MIPS_USES_R4K_TLB #define MIPS_TLB_NB 16 +#define MIPS_TLB_MAX 128 /* basic FPU register support */ #define MIPS_USES_FPU 1 /* Define a implementation number of 1. diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 6e31436f5b..c7d86d0167 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -367,7 +367,7 @@ void do_mtc0 (int reg, int sel) env->CP0_EntryHi = val; /* If the ASID changes, flush qemu's TLB. */ if ((old & 0xFF) != (val & 0xFF)) - tlb_flush (env, 1); + cpu_mips_tlb_flush (env, 1); rn = "EntryHi"; break; case 11: @@ -568,7 +568,14 @@ void fpu_handle_exception(void) /* TLB management */ #if defined(MIPS_USES_R4K_TLB) -static void invalidate_tlb (int idx) +void cpu_mips_tlb_flush (CPUState *env, int flush_global) +{ + /* Flush qemu's TLB and discard all shadowed entries. */ + tlb_flush (env, flush_global); + env->tlb_in_use = MIPS_TLB_NB; +} + +static void invalidate_tlb (int idx, int use_extra) { tlb_t *tlb; target_ulong addr; @@ -583,6 +590,15 @@ static void invalidate_tlb (int idx) return; } + if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) { + /* For tlbwr, we can shadow the discarded entry into + a new (fake) TLB entry, as long as the guest can not + tell that it's there. */ + env->tlb[env->tlb_in_use] = *tlb; + env->tlb_in_use++; + return; + } + if (tlb->V0) { tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN); addr = tlb->VPN; @@ -601,6 +617,14 @@ static void invalidate_tlb (int idx) } } +static void mips_tlb_flush_extra (CPUState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb_in_use > first) { + invalidate_tlb(--env->tlb_in_use, 0); + } +} + static void fill_tlb (int idx) { tlb_t *tlb; @@ -627,9 +651,14 @@ static void fill_tlb (int idx) void do_tlbwi (void) { + /* Discard cached TLB entries. We could avoid doing this if the + tlbwi is just upgrading access permissions on the current entry; + that might be a further win. */ + mips_tlb_flush_extra (env, MIPS_TLB_NB); + /* Wildly undefined effects for CP0_index containing a too high value and MIPS_TLB_NB not being a power of two. But so does real silicon. */ - invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); + invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1), 0); fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); } @@ -637,7 +666,7 @@ void do_tlbwr (void) { int r = cpu_mips_get_random(env); - invalidate_tlb(r); + invalidate_tlb(r, 1); fill_tlb(r); } @@ -660,6 +689,17 @@ void do_tlbp (void) } } if (i == MIPS_TLB_NB) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) { + tlb = &env->tlb[i]; + + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { + mips_tlb_flush_extra (env, i); + break; + } + } + env->CP0_index |= 0x80000000; } } @@ -674,8 +714,10 @@ void do_tlbr (void) tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)]; /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID != tlb->ASID && tlb->G != 1) - tlb_flush (env, 1); + if (ASID != tlb->ASID) + cpu_mips_tlb_flush (env, 1); + + mips_tlb_flush_extra(env, MIPS_TLB_NB); env->CP0_EntryHi = tlb->VPN | tlb->ASID; size = (tlb->end - tlb->VPN) >> 12; diff --git a/target-mips/translate.c b/target-mips/translate.c index f5c3afdce0..0d624185f8 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2430,6 +2430,7 @@ CPUMIPSState *cpu_mips_init (void) env->PC = 0xBFC00000; #if defined (MIPS_USES_R4K_TLB) env->CP0_random = MIPS_TLB_NB - 1; + env->tlb_in_use = MIPS_TLB_NB; #endif env->CP0_Wired = 0; env->CP0_Config0 = MIPS_CONFIG0; |