diff options
| -rw-r--r-- | hw/arm/exynos4210.c | 2 | ||||
| -rw-r--r-- | hw/lm32/milkymist.c | 5 | ||||
| -rw-r--r-- | target/arm/helper.c | 14 | ||||
| -rw-r--r-- | target/arm/translate-a64.c | 8 |
4 files changed, 16 insertions, 13 deletions
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 827318a003..af82e95542 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -162,7 +162,7 @@ static uint64_t exynos4210_calc_affinity(int cpu) Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { - Exynos4210State *s = g_new(Exynos4210State, 1); + Exynos4210State *s = g_new0(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; DeviceState *dev; diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 321f184595..63c6894c95 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -138,7 +138,10 @@ milkymist_init(MachineState *machine) bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (bios_filename) { - load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE); + if (load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE) < 0) { + error_report("could not load bios '%s'", bios_filename); + exit(1); + } } reset_info->bootstrap_pc = BIOS_OFFSET; diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..96301930cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2319,7 +2319,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * * (Note that HCR.DC makes HCR.VM behave as if it is 1.) * - * ATS1Hx always uses the 64bit format (not supported yet). + * ATS1Hx always uses the 64bit format. */ format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); @@ -2347,10 +2347,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ - /* Note that S2WLK and FSTAGE are always zero, because we don't - * implement virtualization and therefore there can't be a stage 2 - * fault. - */ + if (fi.stage2) { + par64 |= (1 << 9); /* S */ + } + if (fi.s1ptw) { + par64 |= (1 << 8); /* PTW */ + } } } else { /* fsr is a DFSR/IFSR value for the short descriptor @@ -2442,7 +2444,7 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; - par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); A32_BANKED_CURRENT_REG_SET(env, par, par64); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 88195ab949..fd36425f1a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9483,12 +9483,10 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, int immhb = immh << 3 | immb; int shift = immhb - (8 << size); - if (extract32(immh, 3, 1) && !is_q) { - unallocated_encoding(s); - return; - } + /* Range of size is limited by decode: immh is a non-zero 4 bit field */ + assert(size >= 0 && size <= 3); - if (size > 3 && !is_q) { + if (extract32(immh, 3, 1) && !is_q) { unallocated_encoding(s); return; } |