diff options
| -rw-r--r-- | target/riscv/cpu.c | 5 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 4 | ||||
| -rw-r--r-- | target/riscv/meson.build | 2 | ||||
| -rw-r--r-- | target/riscv/tcg/meson.build | 2 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 58 |
5 files changed, 67 insertions, 4 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 383e5df2a7..89ce316294 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2284,9 +2284,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" - -static const struct TCGCPUOps riscv_tcg_ops = { +const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, @@ -2445,7 +2443,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; - cc->tcg_ops = &riscv_tcg_ops; object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cce6dee729..1bd736a1a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -707,6 +707,10 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, }; +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ +#include "hw/core/tcg-cpu-ops.h" +extern const struct TCGCPUOps riscv_tcg_ops; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ff60b21d04..b4ded65e41 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -38,5 +38,7 @@ riscv_system_ss.add(files( 'riscv-qmp-cmds.c', )) +subdir('tcg') + target_arch += {'riscv': riscv_ss} target_system_arch += {'riscv': riscv_system_ss} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build new file mode 100644 index 0000000000..061df3d74a --- /dev/null +++ b/target/riscv/tcg/meson.build @@ -0,0 +1,2 @@ +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'tcg-cpu.c')) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c new file mode 100644 index 0000000000..795a8f06b2 --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.c @@ -0,0 +1,58 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" + +static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + /* + * All cpus use the same set of operations. + * riscv_tcg_ops is being imported from cpu.c for now. + */ + cc->tcg_ops = &riscv_tcg_ops; +} + +static void tcg_cpu_class_init(CPUClass *cc) +{ + cc->init_accel_cpu = tcg_cpu_init_ops; +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); + + acc->cpu_class_init = tcg_cpu_class_init; +} + +static const TypeInfo tcg_cpu_accel_type_info = { + .name = ACCEL_CPU_NAME("tcg"), + + .parent = TYPE_ACCEL_CPU, + .class_init = tcg_cpu_accel_class_init, + .abstract = true, +}; + +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); |