diff options
| -rw-r--r-- | target/arm/translate-a64.c | 2 | ||||
| -rw-r--r-- | target/arm/translate.c | 2 | ||||
| -rw-r--r-- | target/arm/translate.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 19c09c3b53..f630384891 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14664,7 +14664,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->isar = &arm_cpu->isar; dc->condjmp = 0; - dc->aarch64 = 1; + dc->aarch64 = true; /* If we are coming from secure EL0 in a system with a 32-bit EL3, then * there is no secure EL1, so we route exceptions to EL3. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 38e7a38f28..6018fee2ef 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9334,7 +9334,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->isar = &cpu->isar; dc->condjmp = 0; - dc->aarch64 = 0; + dc->aarch64 = false; /* If we are coming from secure EL0 in a system with a 32-bit EL3, then * there is no secure EL1, so we route exceptions to EL3. */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 3a0db801d3..8b7dd1a4c0 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -59,12 +59,12 @@ typedef struct DisasContext { * so that top level loop can generate correct syndrome information. */ uint32_t svc_imm; - int aarch64; int current_el; /* Debug target exception level for single-step exceptions */ int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ + bool aarch64; /* Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a single * "is fp access disabled" check at a high level in the decode tree. |