diff options
| -rw-r--r-- | target/arm/cpu.h | 7 | ||||
| -rw-r--r-- | target/arm/tcg/mve_helper.c | 12 | ||||
| -rw-r--r-- | target/arm/tcg/translate-m-nocp.c | 6 | ||||
| -rw-r--r-- | target/arm/tcg/translate-vfp.c | 2 | ||||
| -rw-r--r-- | target/arm/tcg/translate.h | 3 | ||||
| -rw-r--r-- | target/arm/vfp_helper.c | 25 |
6 files changed, 28 insertions, 27 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b1b48c1d77..5323223919 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -619,6 +619,13 @@ typedef struct CPUArchState { int vec_len; int vec_stride; + /* + * Floating point status and control registers. Some bits are + * stored separately in other fields or in the float_status below. + */ + uint64_t fpsr; + uint64_t fpcr; + uint32_t xregs[16]; /* Scratch space for aa32 neon expansion. */ diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 8b99736aad..234f395b09 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -1115,21 +1115,21 @@ static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, if (update_flags) { /* Store C, clear NZV. */ - env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; - env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; + env->vfp.fpsr &= ~FPCR_NZCV_MASK; + env->vfp.fpsr |= carry_in * FPCR_C; } mve_advance_vpt(env); } void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) { - bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; + bool carry_in = env->vfp.fpsr & FPCR_C; do_vadc(env, vd, vn, vm, 0, carry_in, false); } void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) { - bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; + bool carry_in = env->vfp.fpsr & FPCR_C; do_vadc(env, vd, vn, vm, -1, carry_in, false); } @@ -3343,7 +3343,7 @@ static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) uint32_t *m = vm; uint16_t r; uint16_t mask = mve_element_mask(env); - bool ieee = !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + bool ieee = !(env->vfp.fpcr & FPCR_AHP); unsigned e; float_status *fpst; float_status scratch_fpst; @@ -3373,7 +3373,7 @@ static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) uint16_t *m = vm; uint32_t r; uint16_t mask = mve_element_mask(env); - bool ieee = !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + bool ieee = !(env->vfp.fpcr & FPCR_AHP); unsigned e; float_status *fpst; float_status scratch_fpst; diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c index f564d06ccf..875f6a8725 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -341,10 +341,10 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, 16, 16, qc); } tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); - fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + fpscr = load_cpu_field_low32(vfp.fpsr); tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); tcg_gen_or_i32(fpscr, fpscr, tmp); - store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + store_cpu_field_low32(fpscr, vfp.fpsr); break; } case ARM_VFP_FPCXT_NS: @@ -465,7 +465,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, * Read just NZCV; this is a special case to avoid the * helper call for the "VMRS to CPSR.NZCV" insn. */ - tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tmp = load_cpu_field_low32(vfp.fpsr); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp, true); break; diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 39ec971ff7..0d9788e810 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -833,7 +833,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) break; case ARM_VFP_FPSCR: if (a->rt == 15) { - tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tmp = load_cpu_field_low32(vfp.fpsr); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp = tcg_temp_new_i32(); diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index aba21f730f..a8672c857c 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -351,8 +351,7 @@ static inline TCGv_i32 get_ahp_flag(void) { TCGv_i32 ret = tcg_temp_new_i32(); - tcg_gen_ld_i32(ret, tcg_env, - offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); + tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr)); tcg_gen_extract_i32(ret, ret, 26, 1); return ret; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 678de5eb6f..a8c89a910f 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -115,7 +115,7 @@ static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val) static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val) { - uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; + uint64_t changed = env->vfp.fpcr; changed ^= val; if (changed & (3 << 22)) { @@ -175,7 +175,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val) uint32_t vfp_get_fpcr(CPUARMState *env) { - uint32_t fpcr = (env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_MASK) + uint32_t fpcr = env->vfp.fpcr | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); @@ -190,7 +190,7 @@ uint32_t vfp_get_fpcr(CPUARMState *env) uint32_t vfp_get_fpsr(CPUARMState *env) { - uint32_t fpsr = env->vfp.xregs[ARM_VFP_FPSCR] & FPSR_MASK; + uint32_t fpsr = env->vfp.fpsr; uint32_t i; fpsr |= vfp_get_fpsr_from_host(env); @@ -229,15 +229,13 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) } /* - * The only FPSR bits we keep in vfp.xregs[FPSCR] are NZCV: + * The only FPSR bits we keep in vfp.fpsr are NZCV: * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there, - * and zero any of the other FPSR bits (but preserve the FPCR - * bits). + * and zero any of the other FPSR bits. */ val &= FPCR_NZCV_MASK; - env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPSR_MASK; - env->vfp.xregs[ARM_VFP_FPSCR] |= val; + env->vfp.fpsr = val; } void vfp_set_fpcr(CPUARMState *env, uint32_t val) @@ -271,14 +269,13 @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val) * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) * - * The FPCR bits we keep in vfp.xregs[FPSCR] are AHP, DN, FZ, RMode + * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI * bits. */ val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16; - env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_MASK; - env->vfp.xregs[ARM_VFP_FPSCR] |= val; + env->vfp.fpcr = val; } void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) @@ -356,8 +353,7 @@ static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) default: g_assert_not_reached(); } - env->vfp.xregs[ARM_VFP_FPSCR] = - deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); + env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */ } /* XXX: check quiet/signaling case */ @@ -1160,8 +1156,7 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) uint32_t z = (pair >> 32) == 0; /* Store Z, clear NCV, in FPSCR.NZCV. */ - env->vfp.xregs[ARM_VFP_FPSCR] - = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); + env->vfp.fpsr = (env->vfp.fpsr & ~FPCR_NZCV_MASK) | (z * FPCR_Z); return result; } |