diff options
| -rw-r--r-- | hw/openrisc/cputimer.c | 1 | ||||
| -rw-r--r-- | target/openrisc/cpu.c | 3 | ||||
| -rw-r--r-- | target/openrisc/cpu.h | 10 | ||||
| -rw-r--r-- | target/openrisc/interrupt.c | 2 | ||||
| -rw-r--r-- | target/openrisc/machine.c | 1 | ||||
| -rw-r--r-- | target/openrisc/sys_helper.c | 13 |
6 files changed, 29 insertions, 1 deletions
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index a98c799de6..febc469170 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next = now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); + qemu_cpu_kick(CPU(cpu)); } void cpu_openrisc_count_start(OpenRISCCPU *cpu) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f2260e..1d6330cbcc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr = -1; s->exception_index = -1; - cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 938ccc3863..2721432c4f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -140,6 +140,15 @@ enum { IMMUCFGR_HTR = (1 << 11), }; +/* Power management register */ +enum { + PMR_SDF = (15 << 0), + PMR_DME = (1 << 4), + PMR_SME = (1 << 5), + PMR_DCGE = (1 << 6), + PMR_SUME = (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE = 1, @@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2c91fab380..3959671c59 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_SM; env->sr &= ~SR_IEE; env->sr &= ~SR_TEE; + env->pmr &= ~PMR_DME; + env->pmr &= ~PMR_SME; env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62466..a20cce705d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index fa3d6a436e..abdef5d6a5 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" #define TO_SPR(group, number) (((group) << 11) + (number)) @@ -141,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac = deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr = rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC()); + env->pc += 4; + cs->halted = 1; + raise_exception(cpu, EXCP_HALTED); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |= rb; break; @@ -287,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; |