diff options
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/goldfish_pic.c | 8 | ||||
| -rw-r--r-- | hw/intc/i8259_common.c | 14 | ||||
| -rw-r--r-- | hw/intc/ioapic_common.c | 57 | ||||
| -rw-r--r-- | hw/intc/loongarch_ipi.c | 347 | ||||
| -rw-r--r-- | hw/intc/loongson_ipi.c | 125 | ||||
| -rw-r--r-- | hw/intc/m68k_irqc.c | 5 | ||||
| -rw-r--r-- | hw/intc/pnv_xive.c | 38 | ||||
| -rw-r--r-- | hw/intc/pnv_xive2.c | 48 | ||||
| -rw-r--r-- | hw/intc/slavio_intctl.c | 11 | ||||
| -rw-r--r-- | hw/intc/spapr_xive.c | 41 | ||||
| -rw-r--r-- | hw/intc/xics.c | 25 | ||||
| -rw-r--r-- | hw/intc/xics_spapr.c | 7 | ||||
| -rw-r--r-- | hw/intc/xive.c | 108 | ||||
| -rw-r--r-- | hw/intc/xive2.c | 87 |
14 files changed, 289 insertions, 632 deletions
diff --git a/hw/intc/goldfish_pic.c b/hw/intc/goldfish_pic.c index d662dfeb99..6cc1c69d26 100644 --- a/hw/intc/goldfish_pic.c +++ b/hw/intc/goldfish_pic.c @@ -12,7 +12,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "qemu/log.h" #include "trace.h" #include "hw/intc/intc.h" @@ -39,11 +38,12 @@ static bool goldfish_pic_get_statistics(InterruptStatsProvider *obj, return true; } -static void goldfish_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) +static void goldfish_pic_print_info(InterruptStatsProvider *obj, GString *buf) { GoldfishPICState *s = GOLDFISH_PIC(obj); - monitor_printf(mon, "goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n", - s->idx, s->pending, s->enabled); + g_string_append_printf(buf, + "goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n", + s->idx, s->pending, s->enabled); } static void goldfish_pic_update(GoldfishPICState *s) diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index ee0041115c..d9558e3940 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -28,7 +28,6 @@ #include "hw/isa/i8259_internal.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "qapi/error.h" static int irq_level[16]; @@ -132,16 +131,17 @@ static bool pic_get_statistics(InterruptStatsProvider *obj, return true; } -static void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) +static void pic_print_info(InterruptStatsProvider *obj, GString *buf) { PICCommonState *s = PIC_COMMON(obj); pic_dispatch_pre_save(s); - monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " - "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", - s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, - s->irq_base, s->read_reg_select, s->elcr, - s->special_fully_nested_mode); + g_string_append_printf(buf, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " + "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", + s->master ? 0 : 1, s->irr, s->imr, s->isr, + s->priority_add, + s->irq_base, s->read_reg_select, s->elcr, + s->special_fully_nested_mode); } static bool ltim_state_needed(void *opaque) diff --git a/hw/intc/ioapic_common.c b/hw/intc/ioapic_common.c index efbe6958c8..769896353a 100644 --- a/hw/intc/ioapic_common.c +++ b/hw/intc/ioapic_common.c @@ -23,7 +23,6 @@ #include "qapi/error.h" #include "qemu/module.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/intc/ioapic.h" #include "hw/intc/ioapic_internal.h" @@ -59,59 +58,62 @@ static bool ioapic_get_statistics(InterruptStatsProvider *obj, return true; } -static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap) +static void ioapic_irr_dump(GString *buf, const char *name, uint32_t bitmap) { int i; - monitor_printf(mon, "%-10s ", name); + g_string_append_printf(buf, "%-10s ", name); if (bitmap == 0) { - monitor_printf(mon, "(none)\n"); + g_string_append_printf(buf, "(none)\n"); return; } for (i = 0; i < IOAPIC_NUM_PINS; i++) { if (bitmap & (1 << i)) { - monitor_printf(mon, "%-2u ", i); + g_string_append_printf(buf, "%-2u ", i); } } - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } -static void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s) +static void ioapic_print_redtbl(GString *buf, IOAPICCommonState *s) { static const char *delm_str[] = { "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"}; uint32_t remote_irr = 0; int i; - monitor_printf(mon, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x", - s->version, s->id, s->ioregsel); + g_string_append_printf(buf, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x", + s->version, s->id, s->ioregsel); if (s->ioregsel) { - monitor_printf(mon, " (redir[%u])\n", - (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1); + g_string_append_printf(buf, " (redir[%u])\n", + (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1); } else { - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } for (i = 0; i < IOAPIC_NUM_PINS; i++) { uint64_t entry = s->ioredtbl[i]; uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >> IOAPIC_LVT_DELIV_MODE_SHIFT); - monitor_printf(mon, " pin %-2u 0x%016"PRIx64" dest=%"PRIx64 - " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n", - i, entry, - (entry >> IOAPIC_LVT_DEST_SHIFT) & - (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf), - entry & IOAPIC_VECTOR_MASK, - entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi", - entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge", - entry & IOAPIC_LVT_MASKED ? "masked" : "", - delm_str[delm], - entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical"); + g_string_append_printf(buf, " pin %-2u 0x%016"PRIx64" dest=%"PRIx64 + " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n", + i, entry, + (entry >> IOAPIC_LVT_DEST_SHIFT) & + (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf), + entry & IOAPIC_VECTOR_MASK, + entry & IOAPIC_LVT_POLARITY + ? "active-lo" : "active-hi", + entry & IOAPIC_LVT_TRIGGER_MODE + ? "level" : "edge", + entry & IOAPIC_LVT_MASKED ? "masked" : "", + delm_str[delm], + entry & IOAPIC_LVT_DEST_MODE + ? "logical" : "physical"); remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ? (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0; } - ioapic_irr_dump(mon, " IRR", s->irr); - ioapic_irr_dump(mon, " Remote IRR", remote_irr); + ioapic_irr_dump(buf, " IRR", s->irr); + ioapic_irr_dump(buf, " Remote IRR", remote_irr); } void ioapic_reset_common(DeviceState *dev) @@ -171,13 +173,12 @@ static void ioapic_common_realize(DeviceState *dev, Error **errp) ioapic_no++; } -static void ioapic_print_info(InterruptStatsProvider *obj, - Monitor *mon) +static void ioapic_print_info(InterruptStatsProvider *obj, GString *buf) { IOAPICCommonState *s = IOAPIC_COMMON(obj); ioapic_dispatch_pre_save(s); - ioapic_print_redtbl(mon, s); + ioapic_print_redtbl(buf, s); } static const VMStateDescription vmstate_ioapic_common = { diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c deleted file mode 100644 index 44b3b9c138..0000000000 --- a/hw/intc/loongarch_ipi.c +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * LoongArch ipi interrupt support - * - * Copyright (C) 2021 Loongson Technology Corporation Limited - */ - -#include "qemu/osdep.h" -#include "hw/boards.h" -#include "hw/sysbus.h" -#include "hw/intc/loongarch_ipi.h" -#include "hw/irq.h" -#include "hw/qdev-properties.h" -#include "qapi/error.h" -#include "qemu/log.h" -#include "exec/address-spaces.h" -#include "migration/vmstate.h" -#include "target/loongarch/cpu.h" -#include "trace.h" - -static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s; - LoongArchIPI *ipi = opaque; - uint64_t ret = 0; - int index = 0; - - s = &ipi->cpu[attrs.requester_id]; - addr &= 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret = s->status; - break; - case CORE_EN_OFF: - ret = s->en; - break; - case CORE_SET_OFF: - ret = 0; - break; - case CORE_CLEAR_OFF: - ret = 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - ret = s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongarch_ipi_read(size, (uint64_t)addr, ret); - *data = ret; - return MEMTX_OK; -} - -static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr, - MemTxAttrs attrs) -{ - int i, mask = 0, data = 0; - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data = address_space_ldl(env->address_space_iocsr, addr, - attrs, NULL); - for (i = 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |= 0xff << (i * 8); - } - } - } - - data &= mask; - data |= (val >> 32) & ~mask; - address_space_stl(env->address_space_iocsr, addr, - data, attrs, NULL); -} - -static int archid_cmp(const void *a, const void *b) -{ - CPUArchId *archid_a = (CPUArchId *)a; - CPUArchId *archid_b = (CPUArchId *)b; - - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id = id; - found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; -} - -static CPUState *ipi_getcpu(int arch_id) -{ - MachineState *machine = MACHINE(qdev_get_machine()); - CPUArchId *archid; - - archid = find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); - } - - return NULL; -} - -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = ipi_getcpu(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; - send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs); - return MEMTX_OK; -} - -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = ipi_getcpu(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; - send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs); - return MEMTX_OK; -} - -static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - LoongArchIPI *ipi = opaque; - IPICore *s; - int index = 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - s = &ipi->cpu[attrs.requester_id]; - addr &= 0xff; - trace_loongarch_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en = val; - break; - case CORE_SET_OFF: - s->status |= val; - if (s->status != 0 && (s->status & s->en) != 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &= ~val; - if (s->status == 0 && s->en != 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - s->buf[index] = val; - break; - case IOCSR_IPI_SEND: - cpuid = extract32(val, 16, 10); - /* IPI status vector */ - vector = extract8(val, 0, 5); - cs = ipi_getcpu(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - attrs.requester_id = cs->cpu_index; - loongarch_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static const MemoryRegionOps loongarch_ipi_ops = { - .read_with_attrs = loongarch_ipi_readl, - .write_with_attrs = loongarch_ipi_writel, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .valid.min_access_size = 4, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - MemTxResult ret = MEMTX_OK; - - addr &= 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret = mail_send(val, attrs); - break; - case ANY_SEND_OFFSET: - ret = any_send(val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongarch_ipi64_ops = { - .write_with_attrs = loongarch_ipi_writeq, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void loongarch_ipi_realize(DeviceState *dev, Error **errp) -{ - LoongArchIPI *s = LOONGARCH_IPI(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongarch_ipi_ops, - s, "loongarch_ipi_iocsr", 0x48); - - /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard = true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongarch_ipi64_ops, - s, "loongarch_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu = g_new0(IPICore, s->num_cpu); - if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for ExtIOICore faile"); - return; - } - - for (i = 0; i < s->num_cpu; i++) { - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - -static const VMStateDescription vmstate_ipi_core = { - .name = "ipi-single", - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongarch_ipi = { - .name = TYPE_LOONGARCH_IPI, - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchIPI, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongArchIPI, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - -static void loongarch_ipi_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = loongarch_ipi_realize; - device_class_set_props(dc, ipi_properties); - dc->vmsd = &vmstate_loongarch_ipi; -} - -static void loongarch_ipi_finalize(Object *obj) -{ - LoongArchIPI *s = LOONGARCH_IPI(obj); - - g_free(s->cpu); -} - -static const TypeInfo loongarch_ipi_info = { - .name = TYPE_LOONGARCH_IPI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongArchIPI), - .class_init = loongarch_ipi_class_init, - .instance_finalize = loongarch_ipi_finalize, -}; - -static void loongarch_ipi_register_types(void) -{ - type_register_static(&loongarch_ipi_info); -} - -type_init(loongarch_ipi_register_types) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 93cc50a37a..e6a7142480 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -23,16 +23,14 @@ #endif #include "trace.h" -static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) { - IPICore *s; - LoongsonIPI *ipi = opaque; + IPICore *s = opaque; uint64_t ret = 0; int index = 0; - s = &ipi->cpu[attrs.requester_id]; addr &= 0xff; switch (addr) { case CORE_STATUS_OFF: @@ -61,6 +59,21 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, return MEMTX_OK; } +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPI *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) { #ifdef TARGET_LOONGARCH64 @@ -105,39 +118,6 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, return MEMTX_OK; } -static int archid_cmp(const void *a, const void *b) -{ - CPUArchId *archid_a = (CPUArchId *)a; - CPUArchId *archid_b = (CPUArchId *)b; - - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id = id; - found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; -} - -static CPUState *ipi_getcpu(int arch_id) -{ - MachineState *machine = MACHINE(qdev_get_machine()); - CPUArchId *archid; - - archid = find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); - } - - return NULL; -} - static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; @@ -145,7 +125,7 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) CPUState *cs; cpuid = extract32(val, 16, 10); - cs = ipi_getcpu(cpuid); + cs = cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -163,7 +143,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) CPUState *cs; cpuid = extract32(val, 16, 10); - cs = ipi_getcpu(cpuid); + cs = cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -174,17 +154,17 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) return send_ipi_data(cs, val, addr, attrs); } -static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) +static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; - IPICore *s; + IPICore *s = opaque; + LoongsonIPI *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; CPUState *cs; - s = &ipi->cpu[attrs.requester_id]; addr &= 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); switch (addr) { @@ -214,14 +194,12 @@ static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val, cpuid = extract32(val, 16, 10); /* IPI status vector */ vector = extract8(val, 0, 5); - cs = ipi_getcpu(cpuid); - if (cs == NULL) { + cs = cpu_by_arch_id(cpuid); + if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - - /* override requester_id */ - attrs.requester_id = cs->cpu_index; - loongson_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs); + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); break; default: qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); @@ -231,9 +209,34 @@ static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val, return MEMTX_OK; } -static const MemoryRegionOps loongson_ipi_ops = { - .read_with_attrs = loongson_ipi_readl, - .write_with_attrs = loongson_ipi_writel, +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPI *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_core_ops = { + .read_with_attrs = loongson_ipi_core_readl, + .write_with_attrs = loongson_ipi_core_writel, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps loongson_ipi_iocsr_ops = { + .read_with_attrs = loongson_ipi_iocsr_readl, + .write_with_attrs = loongson_ipi_iocsr_writel, .impl.min_access_size = 4, .impl.max_access_size = 4, .valid.min_access_size = 4, @@ -282,7 +285,8 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_ops, + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, s, "loongson_ipi_iocsr", 0x48); /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ @@ -297,11 +301,18 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) s->cpu = g_new0(IPICore, s->num_cpu); if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for ExtIOICore faile"); + error_setg(errp, "Memory allocation for IPICore faile"); return; } for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); + g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c index 4b11fb9f72..cf3beefcfe 100644 --- a/hw/intc/m68k_irqc.c +++ b/hw/intc/m68k_irqc.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "hw/qdev-properties.h" #include "hw/nmi.h" #include "hw/intc/intc.h" @@ -27,10 +26,10 @@ static bool m68k_irqc_get_statistics(InterruptStatsProvider *obj, return true; } -static void m68k_irqc_print_info(InterruptStatsProvider *obj, Monitor *mon) +static void m68k_irqc_print_info(InterruptStatsProvider *obj, GString *buf) { M68KIRQCState *s = M68K_IRQC(obj); - monitor_printf(mon, "m68k-irqc: ipr=0x%x\n", s->ipr); + g_string_append_printf(buf, "m68k-irqc: ipr=0x%x\n", s->ipr); } static void m68k_set_irq(void *opaque, int irq, int level) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index da10deceb8..5bacbce6a4 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -15,7 +15,6 @@ #include "sysemu/cpus.h" #include "sysemu/dma.h" #include "sysemu/reset.h" -#include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_chip.h" @@ -1831,7 +1830,7 @@ static const MemoryRegionOps pnv_xive_pc_ops = { }; static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, - Monitor *mon) + GString *buf) { uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); @@ -1840,12 +1839,12 @@ static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, return; } - monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, - eq_blk, eq_idx, - xive_get_field32(NVT_W4_IPB, nvt->w4)); + g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x\n", + nvt_idx, eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); } -void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) +void pnv_xive_pic_print_info(PnvXive *xive, GString *buf) { XiveRouter *xrtr = XIVE_ROUTER(xive); uint8_t blk = pnv_xive_block_id(xive); @@ -1858,39 +1857,40 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) int i; uint64_t xive_nvt_per_subpage; - monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, - srcno0, srcno0 + nr_ipis - 1); - xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); + g_string_append_printf(buf, "XIVE[%x] #%d Source %08x .. %08x\n", + chip_id, blk, srcno0, srcno0 + nr_ipis - 1); + xive_source_pic_print_info(&xive->ipi_source, srcno0, buf); - monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, - srcno0, srcno0 + nr_ipis - 1); + g_string_append_printf(buf, "XIVE[%x] #%d EAT %08x .. %08x\n", + chip_id, blk, srcno0, srcno0 + nr_ipis - 1); for (i = 0; i < nr_ipis; i++) { if (xive_router_get_eas(xrtr, blk, i, &eas)) { break; } if (!xive_eas_is_masked(&eas)) { - xive_eas_pic_print_info(&eas, i, mon); + xive_eas_pic_print_info(&eas, i, buf); } } - monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); + g_string_append_printf(buf, "XIVE[%x] #%d ENDT\n", chip_id, blk); i = 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { - xive_end_pic_print_info(&end, i++, mon); + xive_end_pic_print_info(&end, i++, buf); } - monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); + g_string_append_printf(buf, "XIVE[%x] #%d END Escalation EAT\n", + chip_id, blk); i = 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { - xive_end_eas_pic_print_info(&end, i++, mon); + xive_end_eas_pic_print_info(&end, i++, buf); } - monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, - 0, XIVE_NVT_COUNT - 1); + g_string_append_printf(buf, "XIVE[%x] #%d NVTT %08x .. %08x\n", + chip_id, blk, 0, XIVE_NVT_COUNT - 1); xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT); for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) { while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { - xive_nvt_pic_print_info(&nvt, i++, mon); + xive_nvt_pic_print_info(&nvt, i++, buf); } } } diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 4b8d0a5d81..2fb4fa29d4 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -13,7 +13,6 @@ #include "target/ppc/cpu.h" #include "sysemu/cpus.h" #include "sysemu/dma.h" -#include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_chip.h" @@ -2027,7 +2026,7 @@ static void pnv_xive2_register_types(void) type_init(pnv_xive2_register_types) static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, - Monitor *mon) + GString *buf) { uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); @@ -2036,21 +2035,21 @@ static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, return; } - monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", - nvp_idx, eq_blk, eq_idx, - xive_get_field32(NVP2_W2_IPB, nvp->w2)); + g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x", + nvp_idx, eq_blk, eq_idx, + xive_get_field32(NVP2_W2_IPB, nvp->w2)); /* * When the NVP is HW controlled, more fields are updated */ if (xive2_nvp_is_hw(nvp)) { - monitor_printf(mon, " CPPR:%02x", - xive_get_field32(NVP2_W2_CPPR, nvp->w2)); + g_string_append_printf(buf, " CPPR:%02x", + xive_get_field32(NVP2_W2_CPPR, nvp->w2)); if (xive2_nvp_is_co(nvp)) { - monitor_printf(mon, " CO:%04x", - xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); + g_string_append_printf(buf, " CO:%04x", + xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); } } - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } /* @@ -2104,7 +2103,7 @@ static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) return (1ull << page_shift) / info->size; } -void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) +void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf) { Xive2Router *xrtr = XIVE2_ROUTER(xive); uint8_t blk = pnv_xive2_block_id(xive); @@ -2117,39 +2116,40 @@ void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) int i; uint64_t xive_nvp_per_subpage; - monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, - srcno0 + nr_esbs - 1); - xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); + g_string_append_printf(buf, "XIVE[%x] Source %08x .. %08x\n", + blk, srcno0, srcno0 + nr_esbs - 1); + xive_source_pic_print_info(&xive->ipi_source, srcno0, buf); - monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, - srcno0 + nr_esbs - 1); + g_string_append_printf(buf, "XIVE[%x] EAT %08x .. %08x\n", + blk, srcno0, srcno0 + nr_esbs - 1); for (i = 0; i < nr_esbs; i++) { if (xive2_router_get_eas(xrtr, blk, i, &eas)) { break; } if (!xive2_eas_is_masked(&eas)) { - xive2_eas_pic_print_info(&eas, i, mon); + xive2_eas_pic_print_info(&eas, i, buf); } } - monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); + g_string_append_printf(buf, "XIVE[%x] #%d END Escalation EAT\n", + chip_id, blk); i = 0; while (!xive2_router_get_end(xrtr, blk, i, &end)) { - xive2_end_eas_pic_print_info(&end, i++, mon); + xive2_end_eas_pic_print_info(&end, i++, buf); } - monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); + g_string_append_printf(buf, "XIVE[%x] #%d ENDT\n", chip_id, blk); i = 0; while (!xive2_router_get_end(xrtr, blk, i, &end)) { - xive2_end_pic_print_info(&end, i++, mon); + xive2_end_pic_print_info(&end, i++, buf); } - monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, - 0, XIVE2_NVP_COUNT - 1); + g_string_append_printf(buf, "XIVE[%x] #%d NVPT %08x .. %08x\n", + chip_id, blk, 0, XIVE2_NVP_COUNT - 1); xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { - xive2_nvp_pic_print_info(&nvp, i++, mon); + xive2_nvp_pic_print_info(&nvp, i++, buf); } } } diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index 36b4a12f60..d6e49d29aa 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "hw/intc/intc.h" @@ -401,17 +400,17 @@ static bool slavio_intctl_get_statistics(InterruptStatsProvider *obj, } #endif -static void slavio_intctl_print_info(InterruptStatsProvider *obj, Monitor *mon) +static void slavio_intctl_print_info(InterruptStatsProvider *obj, GString *buf) { SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); int i; for (i = 0; i < MAX_CPUS; i++) { - monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i, - s->slaves[i].intreg_pending); + g_string_append_printf(buf, "per-cpu %d: pending 0x%08x\n", i, + s->slaves[i].intreg_pending); } - monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n", - s->intregm_pending, s->intregm_disabled); + g_string_append_printf(buf, "master: pending 0x%08x, disabled 0x%08x\n", + s->intregm_pending, s->intregm_disabled); } static void slavio_intctl_init(Object *obj) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d7e56bfb20..283a6b8fd2 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -16,7 +16,6 @@ #include "sysemu/cpus.h" #include "sysemu/reset.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_cpu_core.h" @@ -132,7 +131,7 @@ static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, * structure dumping only the information related to the OS EQ. */ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, - Monitor *mon) + GString *buf) { uint64_t qaddr_base = xive_end_qaddr(end); uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); @@ -142,11 +141,11 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); - monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", - spapr_xive_nvt_to_target(0, nvt), - priority, qindex, qentries, qaddr_base, qgen); + g_string_append_printf(buf, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", + spapr_xive_nvt_to_target(0, nvt), + priority, qindex, qentries, qaddr_base, qgen); - xive_end_queue_pic_print_info(end, 6, mon); + xive_end_queue_pic_print_info(end, 6, buf); } /* @@ -156,7 +155,7 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, #define spapr_xive_in_kernel(xive) \ (kvm_irqchip_in_kernel() && (xive)->fd != -1) -static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) +static void spapr_xive_pic_print_info(SpaprXive *xive, GString *buf) { XiveSource *xsrc = &xive->source; int i; @@ -171,7 +170,7 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) } } - monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); + g_string_append_printf(buf, " LISN PQ EISN CPU/PRIO EQ\n"); for (i = 0; i < xive->nr_irqs; i++) { uint8_t pq = xive_source_esb_get(xsrc, i); @@ -181,13 +180,13 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) continue; } - monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, - xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive_source_is_asserted(xsrc, i) ? 'A' : ' ', - xive_eas_is_masked(eas) ? "M" : " ", - (int) xive_get_field64(EAS_END_DATA, eas->w)); + g_string_append_printf(buf, " %08x %s %c%c%c %s %08x ", i, + xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_source_is_asserted(xsrc, i) ? 'A' : ' ', + xive_eas_is_masked(eas) ? "M" : " ", + (int) xive_get_field64(EAS_END_DATA, eas->w)); if (!xive_eas_is_masked(eas)) { uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); @@ -197,10 +196,11 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) end = &xive->endt[end_idx]; if (xive_end_is_valid(end)) { - spapr_xive_end_pic_print_info(xive, end, mon); + spapr_xive_end_pic_print_info(xive, end, buf); } + } - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } } @@ -699,7 +699,7 @@ static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) } } -static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) +static void spapr_xive_print_info(SpaprInterruptController *intc, GString *buf) { SpaprXive *xive = SPAPR_XIVE(intc); CPUState *cs; @@ -707,10 +707,9 @@ static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); + xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, buf); } - - spapr_xive_pic_print_info(xive, mon); + spapr_xive_pic_print_info(xive, buf); } static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 9b3b7abaea..6f4d5271ea 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -35,14 +35,13 @@ #include "qemu/module.h" #include "qapi/visitor.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "target/ppc/cpu.h" -void icp_pic_print_info(ICPState *icp, Monitor *mon) +void icp_pic_print_info(ICPState *icp, GString *buf) { int cpu_index; @@ -63,17 +62,17 @@ void icp_pic_print_info(ICPState *icp, Monitor *mon) icp_synchronize_state(icp); } - monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", - cpu_index, icp->xirr, icp->xirr_owner, - icp->pending_priority, icp->mfrr); + g_string_append_printf(buf, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", + cpu_index, icp->xirr, icp->xirr_owner, + icp->pending_priority, icp->mfrr); } -void ics_pic_print_info(ICSState *ics, Monitor *mon) +void ics_pic_print_info(ICSState *ics, GString *buf) { uint32_t i; - monitor_printf(mon, "ICS %4x..%4x %p\n", - ics->offset, ics->offset + ics->nr_irqs - 1, ics); + g_string_append_printf(buf, "ICS %4x..%4x %p\n", + ics->offset, ics->offset + ics->nr_irqs - 1, ics); if (!ics->irqs) { return; @@ -89,11 +88,11 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon) if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { continue; } - monitor_printf(mon, " %4x %s %02x %02x\n", - ics->offset + i, - (irq->flags & XICS_FLAGS_IRQ_LSI) ? - "LSI" : "MSI", - irq->priority, irq->status); + g_string_append_printf(buf, " %4x %s %02x %02x\n", + ics->offset + i, + (irq->flags & XICS_FLAGS_IRQ_LSI) ? + "LSI" : "MSI", + irq->priority, irq->status); } } diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 37b2d99977..a0d97bdefe 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -395,7 +395,7 @@ static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val) ics_set_irq(ics, srcno, val); } -static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon) +static void xics_spapr_print_info(SpaprInterruptController *intc, GString *buf) { ICSState *ics = ICS_SPAPR(intc); CPUState *cs; @@ -403,10 +403,9 @@ static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon) CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); + icp_pic_print_info(spapr_cpu_state(cpu)->icp, buf); } - - ics_pic_print_info(ics, mon); + ics_pic_print_info(ics, buf); } static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 057b308ae9..70f11f993b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -17,7 +17,6 @@ #include "sysemu/reset.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "monitor/monitor.h" #include "hw/irq.h" #include "hw/ppc/xive.h" #include "hw/ppc/xive2.h" @@ -669,7 +668,7 @@ static const char * const xive_tctx_ring_names[] = { xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ })) -void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) +void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf) { int cpu_index; int i; @@ -693,13 +692,14 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) } } - monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" - " W2\n", cpu_index); + g_string_append_printf(buf, "CPU[%04x]: " + "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2\n", + cpu_index); for (i = 0; i < XIVE_TM_RING_COUNT; i++) { char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); - monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, - xive_tctx_ring_names[i], s); + g_string_append_printf(buf, "CPU[%04x]: %4s %s\n", + cpu_index, xive_tctx_ring_names[i], s); g_free(s); } } @@ -1207,22 +1207,20 @@ void xive_source_set_irq(void *opaque, int srcno, int val) } } -void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) +void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, GString *buf) { - int i; - - for (i = 0; i < xsrc->nr_irqs; i++) { + for (unsigned i = 0; i < xsrc->nr_irqs; i++) { uint8_t pq = xive_source_esb_get(xsrc, i); if (pq == XIVE_ESB_OFF) { continue; } - monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, - xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive_source_is_asserted(xsrc, i) ? 'A' : ' '); + g_string_append_printf(buf, " %08x %s %c%c%c\n", i + offset, + xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_source_is_asserted(xsrc, i) ? 'A' : ' '); } } @@ -1322,7 +1320,7 @@ static const TypeInfo xive_source_info = { * XiveEND helpers */ -void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) +void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf) { uint64_t qaddr_base = xive_end_qaddr(end); uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); @@ -1333,7 +1331,7 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) /* * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window */ - monitor_printf(mon, " [ "); + g_string_append_printf(buf, " [ "); qindex = (qindex - (width - 1)) & (qentries - 1); for (i = 0; i < width; i++) { uint64_t qaddr = qaddr_base + (qindex << 2); @@ -1345,14 +1343,14 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) HWADDR_PRIx "\n", qaddr); return; } - monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", - be32_to_cpu(qdata)); + g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", + be32_to_cpu(qdata)); qindex = (qindex + 1) & (qentries - 1); } - monitor_printf(mon, "]"); + g_string_append_c(buf, ']'); } -void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) +void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) { uint64_t qaddr_base = xive_end_qaddr(end); uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); @@ -1371,26 +1369,27 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) pq = xive_get_field32(END_W1_ESn, end->w1); - monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", - end_idx, - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive_end_is_valid(end) ? 'v' : '-', - xive_end_is_enqueue(end) ? 'q' : '-', - xive_end_is_notify(end) ? 'n' : '-', - xive_end_is_backlog(end) ? 'b' : '-', - xive_end_is_escalate(end) ? 'e' : '-', - xive_end_is_uncond_escalation(end) ? 'u' : '-', - xive_end_is_silent_escalation(end) ? 's' : '-', - xive_end_is_firmware(end) ? 'f' : '-', - priority, nvt_blk, nvt_idx); + g_string_append_printf(buf, + " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_end_is_valid(end) ? 'v' : '-', + xive_end_is_enqueue(end) ? 'q' : '-', + xive_end_is_notify(end) ? 'n' : '-', + xive_end_is_backlog(end) ? 'b' : '-', + xive_end_is_escalate(end) ? 'e' : '-', + xive_end_is_uncond_escalation(end) ? 'u' : '-', + xive_end_is_silent_escalation(end) ? 's' : '-', + xive_end_is_firmware(end) ? 'f' : '-', + priority, nvt_blk, nvt_idx); if (qaddr_base) { - monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", - qaddr_base, qindex, qentries, qgen); - xive_end_queue_pic_print_info(end, 6, mon); + g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", + qaddr_base, qindex, qentries, qgen); + xive_end_queue_pic_print_info(end, 6, buf); } - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } static void xive_end_enqueue(XiveEND *end, uint32_t data) @@ -1419,8 +1418,7 @@ static void xive_end_enqueue(XiveEND *end, uint32_t data) end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); } -void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, - Monitor *mon) +void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) { XiveEAS *eas = (XiveEAS *) &end->w4; uint8_t pq; @@ -1431,15 +1429,15 @@ void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, pq = xive_get_field32(END_W1_ESe, end->w1); - monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", - end_idx, - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive_eas_is_valid(eas) ? 'V' : ' ', - xive_eas_is_masked(eas) ? 'M' : ' ', - (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), - (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), - (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); + g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_eas_is_valid(eas) ? 'V' : ' ', + xive_eas_is_masked(eas) ? 'M' : ' ', + (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); } /* @@ -1917,17 +1915,17 @@ static const TypeInfo xive_router_info = { } }; -void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) +void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf) { if (!xive_eas_is_valid(eas)) { return; } - monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", - lisn, xive_eas_is_masked(eas) ? "M" : " ", - (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), - (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), - (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); + g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", + lisn, xive_eas_is_masked(eas) ? "M" : " ", + (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); } /* diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 98c0d8ba44..3e7238c663 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -15,7 +15,6 @@ #include "sysemu/cpus.h" #include "sysemu/dma.h" #include "hw/qdev-properties.h" -#include "monitor/monitor.h" #include "hw/ppc/xive.h" #include "hw/ppc/xive2.h" #include "hw/ppc/xive2_regs.h" @@ -27,21 +26,20 @@ uint32_t xive2_router_get_config(Xive2Router *xrtr) return xrc->get_config(xrtr); } -void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon) +void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) { if (!xive2_eas_is_valid(eas)) { return; } - monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", - lisn, xive2_eas_is_masked(eas) ? "M" : " ", - (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), - (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), - (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); + g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", + lisn, xive2_eas_is_masked(eas) ? "M" : " ", + (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); } -void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, - Monitor *mon) +void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) { uint64_t qaddr_base = xive2_end_qaddr(end); uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); @@ -52,7 +50,7 @@ void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, /* * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window */ - monitor_printf(mon, " [ "); + g_string_append_printf(buf, " [ "); qindex = (qindex - (width - 1)) & (qentries - 1); for (i = 0; i < width; i++) { uint64_t qaddr = qaddr_base + (qindex << 2); @@ -64,14 +62,14 @@ void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, HWADDR_PRIx "\n", qaddr); return; } - monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", - be32_to_cpu(qdata)); + g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", + be32_to_cpu(qdata)); qindex = (qindex + 1) & (qentries - 1); } - monitor_printf(mon, "]"); + g_string_append_printf(buf, "]"); } -void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) +void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) { uint64_t qaddr_base = xive2_end_qaddr(end); uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); @@ -90,33 +88,34 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) pq = xive_get_field32(END2_W1_ESn, end->w1); - monitor_printf(mon, - " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", - end_idx, - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive2_end_is_valid(end) ? 'v' : '-', - xive2_end_is_enqueue(end) ? 'q' : '-', - xive2_end_is_notify(end) ? 'n' : '-', - xive2_end_is_backlog(end) ? 'b' : '-', - xive2_end_is_escalate(end) ? 'e' : '-', - xive2_end_is_escalate_end(end) ? 'N' : '-', - xive2_end_is_uncond_escalation(end) ? 'u' : '-', - xive2_end_is_silent_escalation(end) ? 's' : '-', - xive2_end_is_firmware1(end) ? 'f' : '-', - xive2_end_is_firmware2(end) ? 'F' : '-', - priority, nvp_blk, nvp_idx); + g_string_append_printf(buf, + " %08x %c%c %c%c%c%c%c%c%c%c%c%c " + "prio:%d nvp:%02x/%04x", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive2_end_is_valid(end) ? 'v' : '-', + xive2_end_is_enqueue(end) ? 'q' : '-', + xive2_end_is_notify(end) ? 'n' : '-', + xive2_end_is_backlog(end) ? 'b' : '-', + xive2_end_is_escalate(end) ? 'e' : '-', + xive2_end_is_escalate_end(end) ? 'N' : '-', + xive2_end_is_uncond_escalation(end) ? 'u' : '-', + xive2_end_is_silent_escalation(end) ? 's' : '-', + xive2_end_is_firmware1(end) ? 'f' : '-', + xive2_end_is_firmware2(end) ? 'F' : '-', + priority, nvp_blk, nvp_idx); if (qaddr_base) { - monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", - qaddr_base, qindex, qentries, qgen); - xive2_end_queue_pic_print_info(end, 6, mon); + g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", + qaddr_base, qindex, qentries, qgen); + xive2_end_queue_pic_print_info(end, 6, buf); } - monitor_printf(mon, "\n"); + g_string_append_c(buf, '\n'); } void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, - Monitor *mon) + GString *buf) { Xive2Eas *eas = (Xive2Eas *) &end->w4; uint8_t pq; @@ -127,15 +126,15 @@ void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, pq = xive_get_field32(END2_W1_ESe, end->w1); - monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", - end_idx, - pq & XIVE_ESB_VAL_P ? 'P' : '-', - pq & XIVE_ESB_VAL_Q ? 'Q' : '-', - xive2_eas_is_valid(eas) ? 'v' : ' ', - xive2_eas_is_masked(eas) ? 'M' : ' ', - (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), - (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), - (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); + g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive2_eas_is_valid(eas) ? 'v' : ' ', + xive2_eas_is_masked(eas) ? 'M' : ' ', + (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); } static void xive2_end_enqueue(Xive2End *end, uint32_t data) |