diff options
Diffstat (limited to 'hw/riscv/microchip_pfsoc.c')
| -rw-r--r-- | hw/riscv/microchip_pfsoc.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 0b2e9ca175..d8ec973958 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -13,6 +13,7 @@ * 2) eNVM (Embedded Non-Volatile Memory) * 3) MMUARTs (Multi-Mode UART) * 4) Cadence eMMC/SDHC controller and an SD card connected to it + * 5) SiFive Platform DMA (Direct Memory Access Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -71,6 +72,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) TYPE_RISCV_CPU_SIFIVE_U54); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); + object_initialize_child(obj, "dma-controller", &s->dma, + TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); } @@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_PLIC].size); g_free(plic_hart_config); + /* DMA */ + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, + memmap[MICROCHIP_PFSOC_DMA].base); + for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, + qdev_get_gpio_in(DEVICE(s->plic), + MICROCHIP_PFSOC_DMA_IRQ0 + i)); + } + /* SYSREG */ create_unimplemented_device("microchip.pfsoc.sysreg", memmap[MICROCHIP_PFSOC_SYSREG].base, |