diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/elf_ops.h | 218 | ||||
| -rw-r--r-- | hw/magic-load.c | 282 | ||||
| -rw-r--r-- | hw/slavio_intctl.c | 6 | ||||
| -rw-r--r-- | hw/slavio_misc.c | 240 | ||||
| -rw-r--r-- | hw/sun4m.c | 10 | ||||
| -rw-r--r-- | hw/sun4u.c | 254 |
6 files changed, 795 insertions, 215 deletions
diff --git a/hw/elf_ops.h b/hw/elf_ops.h new file mode 100644 index 0000000000..1f3232d47c --- /dev/null +++ b/hw/elf_ops.h @@ -0,0 +1,218 @@ +#ifdef BSWAP_NEEDED +static void glue(bswap_ehdr, SZ)(struct elfhdr *ehdr) +{ + bswap16s(&ehdr->e_type); /* Object file type */ + bswap16s(&ehdr->e_machine); /* Architecture */ + bswap32s(&ehdr->e_version); /* Object file version */ + bswapSZs(&ehdr->e_entry); /* Entry point virtual address */ + bswapSZs(&ehdr->e_phoff); /* Program header table file offset */ + bswapSZs(&ehdr->e_shoff); /* Section header table file offset */ + bswap32s(&ehdr->e_flags); /* Processor-specific flags */ + bswap16s(&ehdr->e_ehsize); /* ELF header size in bytes */ + bswap16s(&ehdr->e_phentsize); /* Program header table entry size */ + bswap16s(&ehdr->e_phnum); /* Program header table entry count */ + bswap16s(&ehdr->e_shentsize); /* Section header table entry size */ + bswap16s(&ehdr->e_shnum); /* Section header table entry count */ + bswap16s(&ehdr->e_shstrndx); /* Section header string table index */ +} + +static void glue(bswap_phdr, SZ)(struct elf_phdr *phdr) +{ + bswap32s(&phdr->p_type); /* Segment type */ + bswapSZs(&phdr->p_offset); /* Segment file offset */ + bswapSZs(&phdr->p_vaddr); /* Segment virtual address */ + bswapSZs(&phdr->p_paddr); /* Segment physical address */ + bswapSZs(&phdr->p_filesz); /* Segment size in file */ + bswapSZs(&phdr->p_memsz); /* Segment size in memory */ + bswap32s(&phdr->p_flags); /* Segment flags */ + bswapSZs(&phdr->p_align); /* Segment alignment */ +} + +static void glue(bswap_shdr, SZ)(struct elf_shdr *shdr) +{ + bswap32s(&shdr->sh_name); + bswap32s(&shdr->sh_type); + bswapSZs(&shdr->sh_flags); + bswapSZs(&shdr->sh_addr); + bswapSZs(&shdr->sh_offset); + bswapSZs(&shdr->sh_size); + bswap32s(&shdr->sh_link); + bswap32s(&shdr->sh_info); + bswapSZs(&shdr->sh_addralign); + bswapSZs(&shdr->sh_entsize); +} + +static void glue(bswap_sym, SZ)(struct elf_sym *sym) +{ + bswap32s(&sym->st_name); + bswapSZs(&sym->st_value); + bswapSZs(&sym->st_size); + bswap16s(&sym->st_shndx); +} +#endif + +static int glue(find_phdr, SZ)(struct elfhdr *ehdr, int fd, struct elf_phdr *phdr, elf_word type) +{ + int i, retval; + + retval = lseek(fd, ehdr->e_phoff, SEEK_SET); + if (retval < 0) + return -1; + + for (i = 0; i < ehdr->e_phnum; i++) { + retval = read(fd, phdr, sizeof(*phdr)); + if (retval < 0) + return -1; + glue(bswap_phdr, SZ)(phdr); + if (phdr->p_type == type) + return 0; + } + return -1; +} + +static void * glue(find_shdr, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, elf_word type) +{ + int i, retval; + + retval = lseek(fd, ehdr->e_shoff, SEEK_SET); + if (retval < 0) + return NULL; + + for (i = 0; i < ehdr->e_shnum; i++) { + retval = read(fd, shdr, sizeof(*shdr)); + if (retval < 0) + return NULL; + glue(bswap_shdr, SZ)(shdr); + if (shdr->sh_type == type) + return qemu_malloc(shdr->sh_size); + } + return NULL; +} + +static void * glue(find_strtab, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab) +{ + int retval; + + retval = lseek(fd, ehdr->e_shoff + sizeof(struct elf_shdr) * symtab->sh_link, SEEK_SET); + if (retval < 0) + return NULL; + + retval = read(fd, shdr, sizeof(*shdr)); + if (retval < 0) + return NULL; + glue(bswap_shdr, SZ)(shdr); + if (shdr->sh_type == SHT_STRTAB) + return qemu_malloc(shdr->sh_size);; + return NULL; +} + +static int glue(read_program, SZ)(int fd, struct elf_phdr *phdr, void *dst, elf_word entry) +{ + int retval; + retval = lseek(fd, phdr->p_offset + entry - phdr->p_vaddr, SEEK_SET); + if (retval < 0) + return -1; + return read(fd, dst, phdr->p_filesz); +} + +static int glue(read_section, SZ)(int fd, struct elf_shdr *s, void *dst) +{ + int retval; + + retval = lseek(fd, s->sh_offset, SEEK_SET); + if (retval < 0) + return -1; + retval = read(fd, dst, s->sh_size); + if (retval < 0) + return -1; + return 0; +} + +static void * glue(process_section, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, elf_word type) +{ + void *dst; + + dst = glue(find_shdr, SZ)(ehdr, fd, shdr, type); + if (!dst) + goto error; + + if (glue(read_section, SZ)(fd, shdr, dst)) + goto error; + return dst; + error: + qemu_free(dst); + return NULL; +} + +static void * glue(process_strtab, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab) +{ + void *dst; + + dst = glue(find_strtab, SZ)(ehdr, fd, shdr, symtab); + if (!dst) + goto error; + + if (glue(read_section, SZ)(fd, shdr, dst)) + goto error; + return dst; + error: + qemu_free(dst); + return NULL; +} + +static void glue(load_symbols, SZ)(struct elfhdr *ehdr, int fd) +{ + struct elf_shdr symtab, strtab; + struct elf_sym *syms; +#if (SZ == 64) + struct elf32_sym *syms32; +#endif + struct syminfo *s; + int nsyms, i; + char *str; + + /* Symbol table */ + syms = glue(process_section, SZ)(ehdr, fd, &symtab, SHT_SYMTAB); + if (!syms) + return; + + nsyms = symtab.sh_size / sizeof(struct elf_sym); +#if (SZ == 64) + syms32 = qemu_mallocz(nsyms * sizeof(struct elf32_sym)); +#endif + for (i = 0; i < nsyms; i++) { + glue(bswap_sym, SZ)(&syms[i]); +#if (SZ == 64) + syms32[i].st_name = syms[i].st_name; + syms32[i].st_info = syms[i].st_info; + syms32[i].st_other = syms[i].st_other; + syms32[i].st_shndx = syms[i].st_shndx; + syms32[i].st_value = syms[i].st_value & 0xffffffff; + syms32[i].st_size = syms[i].st_size & 0xffffffff; +#endif + } + /* String table */ + str = glue(process_strtab, SZ)(ehdr, fd, &strtab, &symtab); + if (!str) + goto error_freesyms; + + /* Commit */ + s = qemu_mallocz(sizeof(*s)); +#if (SZ == 64) + s->disas_symtab = syms32; + qemu_free(syms); +#else + s->disas_symtab = syms; +#endif + s->disas_num_syms = nsyms; + s->disas_strtab = str; + s->next = syminfos; + syminfos = s; + return; + error_freesyms: +#if (SZ == 64) + qemu_free(syms32); +#endif + qemu_free(syms); + return; +} diff --git a/hw/magic-load.c b/hw/magic-load.c index 713343a758..63942c647b 100644 --- a/hw/magic-load.c +++ b/hw/magic-load.c @@ -56,213 +56,49 @@ static void bswap_ahdr(struct exec *e) #include "elf.h" -#ifdef BSWAP_NEEDED -static void bswap_ehdr(Elf32_Ehdr *ehdr) -{ - bswap16s(&ehdr->e_type); /* Object file type */ - bswap16s(&ehdr->e_machine); /* Architecture */ - bswap32s(&ehdr->e_version); /* Object file version */ - bswap32s(&ehdr->e_entry); /* Entry point virtual address */ - bswap32s(&ehdr->e_phoff); /* Program header table file offset */ - bswap32s(&ehdr->e_shoff); /* Section header table file offset */ - bswap32s(&ehdr->e_flags); /* Processor-specific flags */ - bswap16s(&ehdr->e_ehsize); /* ELF header size in bytes */ - bswap16s(&ehdr->e_phentsize); /* Program header table entry size */ - bswap16s(&ehdr->e_phnum); /* Program header table entry count */ - bswap16s(&ehdr->e_shentsize); /* Section header table entry size */ - bswap16s(&ehdr->e_shnum); /* Section header table entry count */ - bswap16s(&ehdr->e_shstrndx); /* Section header string table index */ -} - -static void bswap_phdr(Elf32_Phdr *phdr) -{ - bswap32s(&phdr->p_type); /* Segment type */ - bswap32s(&phdr->p_offset); /* Segment file offset */ - bswap32s(&phdr->p_vaddr); /* Segment virtual address */ - bswap32s(&phdr->p_paddr); /* Segment physical address */ - bswap32s(&phdr->p_filesz); /* Segment size in file */ - bswap32s(&phdr->p_memsz); /* Segment size in memory */ - bswap32s(&phdr->p_flags); /* Segment flags */ - bswap32s(&phdr->p_align); /* Segment alignment */ -} - -static void bswap_shdr(Elf32_Shdr *shdr) -{ - bswap32s(&shdr->sh_name); - bswap32s(&shdr->sh_type); - bswap32s(&shdr->sh_flags); - bswap32s(&shdr->sh_addr); - bswap32s(&shdr->sh_offset); - bswap32s(&shdr->sh_size); - bswap32s(&shdr->sh_link); - bswap32s(&shdr->sh_info); - bswap32s(&shdr->sh_addralign); - bswap32s(&shdr->sh_entsize); -} - -static void bswap_sym(Elf32_Sym *sym) -{ - bswap32s(&sym->st_name); - bswap32s(&sym->st_value); - bswap32s(&sym->st_size); - bswap16s(&sym->st_shndx); -} -#else -#define bswap_ehdr(e) do { } while (0) -#define bswap_phdr(e) do { } while (0) -#define bswap_shdr(e) do { } while (0) -#define bswap_sym(e) do { } while (0) +#ifndef BSWAP_NEEDED +#define bswap_ehdr32(e) do { } while (0) +#define bswap_phdr32(e) do { } while (0) +#define bswap_shdr32(e) do { } while (0) +#define bswap_sym32(e) do { } while (0) +#ifdef TARGET_SPARC64 +#define bswap_ehdr64(e) do { } while (0) +#define bswap_phdr64(e) do { } while (0) +#define bswap_shdr64(e) do { } while (0) +#define bswap_sym64(e) do { } while (0) +#endif #endif -static int find_phdr(struct elfhdr *ehdr, int fd, struct elf_phdr *phdr, uint32_t type) -{ - int i, retval; - - retval = lseek(fd, ehdr->e_phoff, SEEK_SET); - if (retval < 0) - return -1; - - for (i = 0; i < ehdr->e_phnum; i++) { - retval = read(fd, phdr, sizeof(*phdr)); - if (retval < 0) - return -1; - bswap_phdr(phdr); - if (phdr->p_type == type) - return 0; - } - return -1; -} - -static void *find_shdr(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, uint32_t type) -{ - int i, retval; - - retval = lseek(fd, ehdr->e_shoff, SEEK_SET); - if (retval < 0) - return NULL; - - for (i = 0; i < ehdr->e_shnum; i++) { - retval = read(fd, shdr, sizeof(*shdr)); - if (retval < 0) - return NULL; - bswap_shdr(shdr); - if (shdr->sh_type == type) - return qemu_malloc(shdr->sh_size); - } - return NULL; -} - -static void *find_strtab(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab) -{ - int retval; - - retval = lseek(fd, ehdr->e_shoff + sizeof(struct elf_shdr) * symtab->sh_link, SEEK_SET); - if (retval < 0) - return NULL; - - retval = read(fd, shdr, sizeof(*shdr)); - if (retval < 0) - return NULL; - bswap_shdr(shdr); - if (shdr->sh_type == SHT_STRTAB) - return qemu_malloc(shdr->sh_size);; - return NULL; -} - -static int read_program(int fd, struct elf_phdr *phdr, void *dst, uint32_t entry) -{ - int retval; - retval = lseek(fd, phdr->p_offset + entry - phdr->p_vaddr, SEEK_SET); - if (retval < 0) - return -1; - return read(fd, dst, phdr->p_filesz); -} - -static int read_section(int fd, struct elf_shdr *s, void *dst) -{ - int retval; - - retval = lseek(fd, s->sh_offset, SEEK_SET); - if (retval < 0) - return -1; - retval = read(fd, dst, s->sh_size); - if (retval < 0) - return -1; - return 0; -} - -static void *process_section(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, uint32_t type) -{ - void *dst; - - dst = find_shdr(ehdr, fd, shdr, type); - if (!dst) - goto error; - - if (read_section(fd, shdr, dst)) - goto error; - return dst; - error: - qemu_free(dst); - return NULL; -} - -static void *process_strtab(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab) -{ - void *dst; - - dst = find_strtab(ehdr, fd, shdr, symtab); - if (!dst) - goto error; - - if (read_section(fd, shdr, dst)) - goto error; - return dst; - error: - qemu_free(dst); - return NULL; -} - -static void load_symbols(struct elfhdr *ehdr, int fd) -{ - struct elf_shdr symtab, strtab; - struct elf_sym *syms; - struct syminfo *s; - int nsyms, i; - char *str; - - /* Symbol table */ - syms = process_section(ehdr, fd, &symtab, SHT_SYMTAB); - if (!syms) - return; - - nsyms = symtab.sh_size / sizeof(struct elf_sym); - for (i = 0; i < nsyms; i++) - bswap_sym(&syms[i]); - - /* String table */ - str = process_strtab(ehdr, fd, &strtab, &symtab); - if (!str) - goto error_freesyms; - - /* Commit */ - s = qemu_mallocz(sizeof(*s)); - s->disas_symtab = syms; - s->disas_num_syms = nsyms; - s->disas_strtab = str; - s->next = syminfos; - syminfos = s; - return; - error_freesyms: - qemu_free(syms); - return; -} +#define SZ 32 +#define elf_word uint32_t +#define bswapSZs bswap32s +#include "elf_ops.h" + +#ifdef TARGET_SPARC64 +#undef elfhdr +#undef elf_phdr +#undef elf_shdr +#undef elf_sym +#undef elf_note +#undef elf_word +#undef bswapSZs +#undef SZ +#define elfhdr elf64_hdr +#define elf_phdr elf64_phdr +#define elf_note elf64_note +#define elf_shdr elf64_shdr +#define elf_sym elf64_sym +#define elf_word uint64_t +#define bswapSZs bswap64s +#define SZ 64 +#include "elf_ops.h" +#endif int load_elf(const char *filename, uint8_t *addr) { - struct elfhdr ehdr; - struct elf_phdr phdr; + struct elf32_hdr ehdr; int retval, fd; + Elf32_Half machine; fd = open(filename, O_RDONLY | O_BINARY); if (fd < 0) @@ -272,21 +108,43 @@ int load_elf(const char *filename, uint8_t *addr) if (retval < 0) goto error; - bswap_ehdr(&ehdr); - if (ehdr.e_ident[0] != 0x7f || ehdr.e_ident[1] != 'E' - || ehdr.e_ident[2] != 'L' || ehdr.e_ident[3] != 'F' - || (ehdr.e_machine != EM_SPARC - && ehdr.e_machine != EM_SPARC32PLUS)) + || ehdr.e_ident[2] != 'L' || ehdr.e_ident[3] != 'F') goto error; + machine = tswap16(ehdr.e_machine); + if (machine == EM_SPARC || machine == EM_SPARC32PLUS) { + struct elf32_phdr phdr; - if (find_phdr(&ehdr, fd, &phdr, PT_LOAD)) - goto error; - retval = read_program(fd, &phdr, addr, ehdr.e_entry); - if (retval < 0) - goto error; + bswap_ehdr32(&ehdr); - load_symbols(&ehdr, fd); + if (find_phdr32(&ehdr, fd, &phdr, PT_LOAD)) + goto error; + retval = read_program32(fd, &phdr, addr, ehdr.e_entry); + if (retval < 0) + goto error; + load_symbols32(&ehdr, fd); + } +#ifdef TARGET_SPARC64 + else if (machine == EM_SPARCV9) { + struct elf64_hdr ehdr64; + struct elf64_phdr phdr; + + lseek(fd, 0, SEEK_SET); + + retval = read(fd, &ehdr64, sizeof(ehdr64)); + if (retval < 0) + goto error; + + bswap_ehdr64(&ehdr64); + + if (find_phdr64(&ehdr64, fd, &phdr, PT_LOAD)) + goto error; + retval = read_program64(fd, &phdr, addr, ehdr64.e_entry); + if (retval < 0) + goto error; + load_symbols64(&ehdr64, fd); + } +#endif close(fd); return retval; diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 9c8ddd0d0c..8a5db5c3cd 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -144,14 +144,14 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin switch (saddr) { case 2: // clear (enable) // Force clear unused bits - val &= ~0x7fb2007f; + val &= ~0x4fb2007f; s->intregm_disabled &= ~val; DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); slavio_check_interrupts(s); break; case 3: // set (disable, clear pending) // Force clear unused bits - val &= ~0x7fb2007f; + val &= ~0x4fb2007f; s->intregm_disabled |= val; s->intregm_pending &= ~val; DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); @@ -208,7 +208,7 @@ void slavio_irq_info(void *opaque) static const uint32_t intbit_to_level[32] = { 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 0, 0, + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, }; static void slavio_check_interrupts(void *opaque) diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c new file mode 100644 index 0000000000..597a0cb127 --- /dev/null +++ b/hw/slavio_misc.c @@ -0,0 +1,240 @@ +/* + * QEMU Sparc SLAVIO aux io port emulation + * + * Copyright (c) 2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "vl.h" +/* debug misc */ +//#define DEBUG_MISC + +/* + * This is the auxio port, chip control and system control part of + * chip STP2001 (Slave I/O), also produced as NCR89C105. See + * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt + * + * This also includes the PMC CPU idle controller. + */ + +#ifdef DEBUG_MISC +#define MISC_DPRINTF(fmt, args...) \ +do { printf("MISC: " fmt , ##args); } while (0) +#else +#define MISC_DPRINTF(fmt, args...) +#endif + +typedef struct MiscState { + int irq; + uint8_t config; + uint8_t aux1, aux2; + uint8_t diag, mctrl; +} MiscState; + +#define MISC_MAXADDR 1 + +static void slavio_misc_update_irq(void *opaque) +{ + MiscState *s = opaque; + + if ((s->aux2 & 0x4) && (s->config & 0x8)) { + pic_set_irq(s->irq, 1); + } else { + pic_set_irq(s->irq, 0); + } +} + +static void slavio_misc_reset(void *opaque) +{ + MiscState *s = opaque; + + // Diagnostic register not cleared in reset + s->config = s->aux1 = s->aux2 = s->mctrl = 0; +} + +void slavio_set_power_fail(void *opaque, int power_failing) +{ + MiscState *s = opaque; + + MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); + if (power_failing && (s->config & 0x8)) { + s->aux2 |= 0x4; + } else { + s->aux2 &= ~0x4; + } + slavio_misc_update_irq(s); +} + +static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +{ + MiscState *s = opaque; + + switch (addr & 0xfff0000) { + case 0x1800000: + MISC_DPRINTF("Write config %2.2x\n", val & 0xff); + s->config = val & 0xff; + slavio_misc_update_irq(s); + break; + case 0x1900000: + MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); + s->aux1 = val & 0xff; + break; + case 0x1910000: + val &= 0x3; + MISC_DPRINTF("Write aux2 %2.2x\n", val); + val |= s->aux2 & 0x4; + if (val & 0x2) // Clear Power Fail int + val &= 0x1; + s->aux2 = val; + if (val & 1) + qemu_system_shutdown_request(); + slavio_misc_update_irq(s); + break; + case 0x1a00000: + MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); + s->diag = val & 0xff; + break; + case 0x1b00000: + MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); + s->mctrl = val & 0xff; + break; + case 0x1f00000: + MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); + if (val & 1) + qemu_system_reset_request(); + break; + case 0xa000000: + MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); +#if 0 + // XXX: halting CPU does not work + raise_exception(EXCP_HLT); + cpu_loop_exit(); +#endif + break; + } +} + +static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) +{ + MiscState *s = opaque; + uint32_t ret = 0; + + switch (addr & 0xfff0000) { + case 0x1800000: + ret = s->config; + MISC_DPRINTF("Read config %2.2x\n", ret); + break; + case 0x1900000: + ret = s->aux1; + MISC_DPRINTF("Read aux1 %2.2x\n", ret); + break; + case 0x1910000: + ret = s->aux2; + MISC_DPRINTF("Read aux2 %2.2x\n", ret); + break; + case 0x1a00000: + ret = s->diag; + MISC_DPRINTF("Read diag %2.2x\n", ret); + break; + case 0x1b00000: + ret = s->mctrl; + MISC_DPRINTF("Read modem control %2.2x\n", ret); + break; + case 0x1f00000: + MISC_DPRINTF("Read system control %2.2x\n", ret); + break; + case 0xa000000: + MISC_DPRINTF("Read power management %2.2x\n", ret); + break; + } + return ret; +} + +static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { + slavio_misc_mem_readb, + slavio_misc_mem_readb, + slavio_misc_mem_readb, +}; + +static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { + slavio_misc_mem_writeb, + slavio_misc_mem_writeb, + slavio_misc_mem_writeb, +}; + +static void slavio_misc_save(QEMUFile *f, void *opaque) +{ + MiscState *s = opaque; + + qemu_put_be32s(f, &s->irq); + qemu_put_8s(f, &s->config); + qemu_put_8s(f, &s->aux1); + qemu_put_8s(f, &s->aux2); + qemu_put_8s(f, &s->diag); + qemu_put_8s(f, &s->mctrl); +} + +static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) +{ + MiscState *s = opaque; + + if (version_id != 1) + return -EINVAL; + + qemu_get_be32s(f, &s->irq); + qemu_get_8s(f, &s->config); + qemu_get_8s(f, &s->aux1); + qemu_get_8s(f, &s->aux2); + qemu_get_8s(f, &s->diag); + qemu_get_8s(f, &s->mctrl); + return 0; +} + +void *slavio_misc_init(uint32_t base, int irq) +{ + int slavio_misc_io_memory; + MiscState *s; + + s = qemu_mallocz(sizeof(MiscState)); + if (!s) + return NULL; + + slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s); + // Slavio control + cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory); + // AUX 1 + cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory); + // AUX 2 + cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory); + // Diagnostics + cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory); + // Modem control + cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory); + // System control + cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory); + // Power management + cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory); + + s->irq = irq; + + register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s); + qemu_register_reset(slavio_misc_reset, s); + slavio_misc_reset(s); + return s; +} diff --git a/hw/sun4m.c b/hw/sun4m.c index 397ade4cbf..56b9069e57 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -37,6 +37,7 @@ // bits #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ +#define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */ #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ #define PHYS_JJ_ESP_IRQ 18 @@ -55,6 +56,7 @@ #define PHYS_JJ_SER_IRQ 15 #define PHYS_JJ_FDC 0x71400000 /* Floppy */ #define PHYS_JJ_FLOPPY_IRQ 22 +#define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */ /* TSC handling */ @@ -202,6 +204,13 @@ uint32_t iommu_translate(uint32_t addr) return iommu_translate_local(iommu, addr); } +static void *slavio_misc; + +void qemu_system_powerdown(void) +{ + slavio_set_power_fail(slavio_misc, 1); +} + /* Sun4m hardware initialisation */ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, @@ -230,6 +239,7 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); + slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ); prom_offset = ram_size + vram_size; diff --git a/hw/sun4u.c b/hw/sun4u.c new file mode 100644 index 0000000000..af15464212 --- /dev/null +++ b/hw/sun4u.c @@ -0,0 +1,254 @@ +/* + * QEMU Sun4u System Emulator + * + * Copyright (c) 2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "vl.h" +#include "m48t08.h" + +#define KERNEL_LOAD_ADDR 0x00004000 +#define CMDLINE_ADDR 0x007ff000 +#define INITRD_LOAD_ADDR 0x00800000 +#define PROM_ADDR 0xffd00000 +#define PROM_FILENAMEB "proll-sparc64.bin" +#define PROM_FILENAMEE "proll-sparc64.elf" +#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ +#define PHYS_JJ_IDPROM_OFF 0x1FD8 +#define PHYS_JJ_EEPROM_SIZE 0x2000 +// IRQs are not PIL ones, but master interrupt controller register +// bits +#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ +#define PHYS_JJ_MS_KBD_IRQ 14 +#define PHYS_JJ_SER 0x71100000 /* Serial */ +#define PHYS_JJ_SER_IRQ 15 + +/* TSC handling */ + +uint64_t cpu_get_tsc() +{ + return qemu_get_clock(vm_clock); +} + +int DMA_get_channel_mode (int nchan) +{ + return 0; +} +int DMA_read_memory (int nchan, void *buf, int pos, int size) +{ + return 0; +} +int DMA_write_memory (int nchan, void *buf, int pos, int size) +{ + return 0; +} +void DMA_hold_DREQ (int nchan) {} +void DMA_release_DREQ (int nchan) {} +void DMA_schedule(int nchan) {} +void DMA_run (void) {} +void DMA_init (int high_page_enable) {} +void DMA_register_channel (int nchan, + DMA_transfer_handler transfer_handler, + void *opaque) +{ +} + +static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) +{ + m48t08_write(nvram, addr++, (value >> 8) & 0xff); + m48t08_write(nvram, addr++, value & 0xff); +} + +static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) +{ + m48t08_write(nvram, addr++, value >> 24); + m48t08_write(nvram, addr++, (value >> 16) & 0xff); + m48t08_write(nvram, addr++, (value >> 8) & 0xff); + m48t08_write(nvram, addr++, value & 0xff); +} + +static void nvram_set_string (m48t08_t *nvram, uint32_t addr, + const unsigned char *str, uint32_t max) +{ + unsigned int i; + + for (i = 0; i < max && str[i] != '\0'; i++) { + m48t08_write(nvram, addr + i, str[i]); + } + m48t08_write(nvram, addr + max - 1, '\0'); +} + +static m48t08_t *nvram; + +extern int nographic; + +static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, + int boot_device, uint32_t RAM_size, + uint32_t kernel_size, + int width, int height, int depth) +{ + unsigned char tmp = 0; + int i, j; + + // Try to match PPC NVRAM + nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); + nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ + // NVRAM_size, arch not applicable + m48t08_write(nvram, 0x2F, nographic & 0xff); + nvram_set_lword(nvram, 0x30, RAM_size); + m48t08_write(nvram, 0x34, boot_device & 0xff); + nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); + nvram_set_lword(nvram, 0x3C, kernel_size); + if (cmdline) { + strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); + nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); + nvram_set_lword(nvram, 0x44, strlen(cmdline)); + } + // initrd_image, initrd_size passed differently + nvram_set_word(nvram, 0x54, width); + nvram_set_word(nvram, 0x56, height); + nvram_set_word(nvram, 0x58, depth); + + // Sun4m specific use + i = 0x1fd8; + m48t08_write(nvram, i++, 0x01); + m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ + j = 0; + m48t08_write(nvram, i++, macaddr[j++]); + m48t08_write(nvram, i++, macaddr[j++]); + m48t08_write(nvram, i++, macaddr[j++]); + m48t08_write(nvram, i++, macaddr[j++]); + m48t08_write(nvram, i++, macaddr[j++]); + m48t08_write(nvram, i, macaddr[j]); + + /* Calculate checksum */ + for (i = 0x1fd8; i < 0x1fe7; i++) { + tmp ^= m48t08_read(nvram, i); + } + m48t08_write(nvram, 0x1fe7, tmp); +} + +void pic_info() +{ +} + +void irq_info() +{ +} + +void pic_set_irq(int irq, int level) +{ +} + +void vga_update_display() +{ +} + +void vga_invalidate_display() +{ +} + +void vga_screen_dump(const char *filename) +{ +} + +void qemu_system_powerdown(void) +{ +} + +/* Sun4u hardware initialisation */ +static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, + DisplayState *ds, const char **fd_filename, int snapshot, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename) +{ + char buf[1024]; + int ret, linux_boot; + unsigned int i; + long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; + + linux_boot = (kernel_filename != NULL); + + /* allocate RAM */ + cpu_register_physical_memory(0, ram_size, 0); + + nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); + // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device + // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device + slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); + + prom_offset = ram_size + vram_size; + + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); + ret = load_elf(buf, phys_ram_base + prom_offset); + if (ret < 0) { + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); + ret = load_image(buf, phys_ram_base + prom_offset); + } + if (ret < 0) { + fprintf(stderr, "qemu: could not load prom '%s'\n", + buf); + exit(1); + } + cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, + prom_offset | IO_MEM_ROM); + + kernel_size = 0; + if (linux_boot) { + kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + if (kernel_size < 0) + kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + if (kernel_size < 0) + kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + + /* load initrd */ + initrd_size = 0; + if (initrd_filename) { + initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); + if (initrd_size < 0) { + fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", + initrd_filename); + exit(1); + } + } + if (initrd_size > 0) { + for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { + if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) + == 0x48647253) { // HdrS + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); + break; + } + } + } + } + nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); +} + +QEMUMachine sun4u_machine = { + "sun4u", + "Sun4u platform", + sun4u_init, +}; |