diff options
Diffstat (limited to 'include/hw/i386')
| -rw-r--r-- | include/hw/i386/ich9.h | 252 | ||||
| -rw-r--r-- | include/hw/i386/ioapic.h | 33 | ||||
| -rw-r--r-- | include/hw/i386/ioapic_internal.h | 118 | ||||
| -rw-r--r-- | include/hw/i386/pc.h | 3 | ||||
| -rw-r--r-- | include/hw/i386/x86.h | 6 |
5 files changed, 4 insertions, 408 deletions
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h deleted file mode 100644 index 222781e8b9..0000000000 --- a/include/hw/i386/ich9.h +++ /dev/null @@ -1,252 +0,0 @@ -#ifndef HW_ICH9_H -#define HW_ICH9_H - -#include "hw/isa/isa.h" -#include "hw/sysbus.h" -#include "hw/i386/pc.h" -#include "hw/isa/apm.h" -#include "hw/acpi/acpi.h" -#include "hw/acpi/ich9.h" -#include "qom/object.h" - -void ich9_lpc_set_irq(void *opaque, int irq_num, int level); -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); -void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled); -I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base); - -void ich9_generate_smi(void); - -#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ - -#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" -OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) - -struct ICH9LPCState { - /* ICH9 LPC PCI to ISA bridge */ - PCIDevice d; - - /* (pci device, intx) -> pirq - * In real chipset case, the unused slots are never used - * as ICH9 supports only D25-D31 irq routing. - * On the other hand in qemu case, any slot/function can be populated - * via command line option. - * So fallback interrupt routing for any devices in any slots is necessary. - */ - uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; - - APMState apm; - ICH9LPCPMRegs pm; - uint32_t sci_level; /* track sci level */ - uint8_t sci_gsi; - - /* 2.24 Pin Straps */ - struct { - bool spkr_hi; - } pin_strap; - - /* 10.1 Chipset Configuration registers(Memory Space) - which is pointed by RCBA */ - uint8_t chip_config[ICH9_CC_SIZE]; - - /* - * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) - * - * register contents and IO memory region - */ - uint8_t rst_cnt; - MemoryRegion rst_cnt_mem; - - /* SMI feature negotiation via fw_cfg */ - uint64_t smi_host_features; /* guest-invisible, host endian */ - uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little - * endian uint64_t */ - uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little - * endian uint64_t */ - uint8_t smi_features_ok; /* guest-visible, read-only; selecting it - * triggers feature lockdown */ - uint64_t smi_negotiated_features; /* guest-invisible, host endian */ - - /* isa bus */ - ISABus *isa_bus; - MemoryRegion rcrb_mem; /* root complex register block */ - Notifier machine_ready; - - qemu_irq gsi[GSI_NUM_PINS]; -}; - -#define Q35_MASK(bit, ms_bit, ls_bit) \ -((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) - -/* ICH9: Chipset Configuration Registers */ -#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) - -#define ICH9_CC -#define ICH9_CC_D28IP 0x310C -#define ICH9_CC_D28IP_SHIFT 4 -#define ICH9_CC_D28IP_MASK 0xf -#define ICH9_CC_D28IP_DEFAULT 0x00214321 -#define ICH9_CC_D31IR 0x3140 -#define ICH9_CC_D30IR 0x3142 -#define ICH9_CC_D29IR 0x3144 -#define ICH9_CC_D28IR 0x3146 -#define ICH9_CC_D27IR 0x3148 -#define ICH9_CC_D26IR 0x314C -#define ICH9_CC_D25IR 0x3150 -#define ICH9_CC_DIR_DEFAULT 0x3210 -#define ICH9_CC_D30IR_DEFAULT 0x0 -#define ICH9_CC_DIR_SHIFT 4 -#define ICH9_CC_DIR_MASK 0x7 -#define ICH9_CC_OIC 0x31FF -#define ICH9_CC_OIC_AEN 0x1 -#define ICH9_CC_GCS 0x3410 -#define ICH9_CC_GCS_DEFAULT 0x00000020 -#define ICH9_CC_GCS_NO_REBOOT (1 << 5) - -/* D28:F[0-5] */ -#define ICH9_PCIE_DEV 28 -#define ICH9_PCIE_FUNC_MAX 6 - - -/* D29:F0 USB UHCI Controller #1 */ -#define ICH9_USB_UHCI1_DEV 29 -#define ICH9_USB_UHCI1_FUNC 0 - -/* D30:F0 DMI-to-PCI bridge */ -#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" -#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 - -#define ICH9_D2P_BRIDGE_DEV 30 -#define ICH9_D2P_BRIDGE_FUNC 0 - -#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) - -#define ICH9_D2P_A2_REVISION 0x92 - -/* D31:F0 LPC Processor Interface */ -#define ICH9_RST_CNT_IOPORT 0xCF9 - -/* D31:F1 LPC controller */ -#define ICH9_A2_LPC "ICH9 A2 LPC" -#define ICH9_A2_LPC_SAVEVM_VERSION 0 - -#define ICH9_LPC_DEV 31 -#define ICH9_LPC_FUNC 0 - -#define ICH9_A2_LPC_REVISION 0x2 -#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ - -#define ICH9_LPC_PMBASE 0x40 -#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) -#define ICH9_LPC_PMBASE_RTE 0x1 -#define ICH9_LPC_PMBASE_DEFAULT 0x1 - -#define ICH9_LPC_ACPI_CTRL 0x44 -#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 -#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) -#define ICH9_LPC_ACPI_CTRL_9 0x0 -#define ICH9_LPC_ACPI_CTRL_10 0x1 -#define ICH9_LPC_ACPI_CTRL_11 0x2 -#define ICH9_LPC_ACPI_CTRL_20 0x4 -#define ICH9_LPC_ACPI_CTRL_21 0x5 -#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 - -#define ICH9_LPC_PIRQA_ROUT 0x60 -#define ICH9_LPC_PIRQB_ROUT 0x61 -#define ICH9_LPC_PIRQC_ROUT 0x62 -#define ICH9_LPC_PIRQD_ROUT 0x63 - -#define ICH9_LPC_PIRQE_ROUT 0x68 -#define ICH9_LPC_PIRQF_ROUT 0x69 -#define ICH9_LPC_PIRQG_ROUT 0x6a -#define ICH9_LPC_PIRQH_ROUT 0x6b - -#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 -#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) -#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 - -#define ICH9_LPC_GEN_PMCON_1 0xa0 -#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) -#define ICH9_LPC_GEN_PMCON_2 0xa2 -#define ICH9_LPC_GEN_PMCON_3 0xa4 -#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 - -#define ICH9_LPC_RCBA 0xf0 -#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) -#define ICH9_LPC_RCBA_EN 0x1 -#define ICH9_LPC_RCBA_DEFAULT 0x0 - -#define ICH9_LPC_PIC_NUM_PINS 16 -#define ICH9_LPC_IOAPIC_NUM_PINS 24 - -#define ICH9_GPIO_GSI "gsi" - -/* D31:F2 SATA Controller #1 */ -#define ICH9_SATA1_DEV 31 -#define ICH9_SATA1_FUNC 2 - -/* D31:F0 power management I/O registers - offset from the address ICH9_LPC_PMBASE */ - -/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ -#define ICH9_PMIO_SIZE 128 -#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) - -#define ICH9_PMIO_PM1_STS 0x00 -#define ICH9_PMIO_PM1_EN 0x02 -#define ICH9_PMIO_PM1_CNT 0x04 -#define ICH9_PMIO_PM1_TMR 0x08 -#define ICH9_PMIO_GPE0_STS 0x20 -#define ICH9_PMIO_GPE0_EN 0x28 -#define ICH9_PMIO_GPE0_LEN 16 -#define ICH9_PMIO_SMI_EN 0x30 -#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) -#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) -#define ICH9_PMIO_SMI_STS 0x34 -#define ICH9_PMIO_TCO_RLD 0x60 -#define ICH9_PMIO_TCO_LEN 32 - -/* FADT ACPI_ENABLE/ACPI_DISABLE */ -#define ICH9_APM_ACPI_ENABLE 0x2 -#define ICH9_APM_ACPI_DISABLE 0x3 - - -/* D31:F3 SMBus controller */ -#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" - -#define ICH9_A2_SMB_REVISION 0x02 -#define ICH9_SMB_PI 0x00 - -#define ICH9_SMB_SMBMBAR0 0x10 -#define ICH9_SMB_SMBMBAR1 0x14 -#define ICH9_SMB_SMBM_BAR 0 -#define ICH9_SMB_SMBM_SIZE (1 << 8) -#define ICH9_SMB_SMB_BASE 0x20 -#define ICH9_SMB_SMB_BASE_BAR 4 -#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) -#define ICH9_SMB_HOSTC 0x40 -#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) -#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) -#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) -#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) - -/* D31:F3 SMBus I/O and memory mapped I/O registers */ -#define ICH9_SMB_DEV 31 -#define ICH9_SMB_FUNC 3 - -#define ICH9_SMB_HST_STS 0x00 -#define ICH9_SMB_HST_CNT 0x02 -#define ICH9_SMB_HST_CMD 0x03 -#define ICH9_SMB_XMIT_SLVA 0x04 -#define ICH9_SMB_HST_D0 0x05 -#define ICH9_SMB_HST_D1 0x06 -#define ICH9_SMB_HOST_BLOCK_DB 0x07 - -#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" - -/* bit positions used in fw_cfg SMI feature negotiation */ -#define ICH9_LPC_SMI_F_BROADCAST_BIT 0 -#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 -#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 - -#endif /* HW_ICH9_H */ diff --git a/include/hw/i386/ioapic.h b/include/hw/i386/ioapic.h deleted file mode 100644 index ef37b8a9fd..0000000000 --- a/include/hw/i386/ioapic.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * ioapic.c IOAPIC emulation logic - * - * Copyright (c) 2011 Jan Kiszka, Siemens AG - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef HW_IOAPIC_H -#define HW_IOAPIC_H - -#define IOAPIC_NUM_PINS 24 -#define IO_APIC_DEFAULT_ADDRESS 0xfec00000 -#define IO_APIC_SECONDARY_ADDRESS (IO_APIC_DEFAULT_ADDRESS + 0x10000) -#define IO_APIC_SECONDARY_IRQBASE 24 /* primary 0 -> 23, secondary 24 -> 47 */ - -#define TYPE_KVM_IOAPIC "kvm-ioapic" -#define TYPE_IOAPIC "ioapic" - -void ioapic_eoi_broadcast(int vector); - -#endif /* HW_IOAPIC_H */ diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h deleted file mode 100644 index e8ff338d7f..0000000000 --- a/include/hw/i386/ioapic_internal.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * IOAPIC emulation logic - internal interfaces - * - * Copyright (c) 2004-2005 Fabrice Bellard - * Copyright (c) 2009 Xiantao Zhang, Intel - * Copyright (c) 2011 Jan Kiszka, Siemens AG - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef QEMU_IOAPIC_INTERNAL_H -#define QEMU_IOAPIC_INTERNAL_H - -#include "exec/memory.h" -#include "hw/i386/ioapic.h" -#include "hw/sysbus.h" -#include "qemu/notify.h" -#include "qom/object.h" - -#define MAX_IOAPICS 2 - -#define IOAPIC_LVT_DEST_SHIFT 56 -#define IOAPIC_LVT_DEST_IDX_SHIFT 48 -#define IOAPIC_LVT_MASKED_SHIFT 16 -#define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15 -#define IOAPIC_LVT_REMOTE_IRR_SHIFT 14 -#define IOAPIC_LVT_POLARITY_SHIFT 13 -#define IOAPIC_LVT_DELIV_STATUS_SHIFT 12 -#define IOAPIC_LVT_DEST_MODE_SHIFT 11 -#define IOAPIC_LVT_DELIV_MODE_SHIFT 8 - -#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT) -#define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT) -#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT) -#define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT) -#define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT) -#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT) -#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT) - -/* Bits that are read-only for IOAPIC entry */ -#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \ - IOAPIC_LVT_DELIV_STATUS) -#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS) - -#define IOAPIC_TRIGGER_EDGE 0 -#define IOAPIC_TRIGGER_LEVEL 1 - -/*io{apic,sapic} delivery mode*/ -#define IOAPIC_DM_FIXED 0x0 -#define IOAPIC_DM_LOWEST_PRIORITY 0x1 -#define IOAPIC_DM_PMI 0x2 -#define IOAPIC_DM_NMI 0x4 -#define IOAPIC_DM_INIT 0x5 -#define IOAPIC_DM_SIPI 0x6 -#define IOAPIC_DM_EXTINT 0x7 -#define IOAPIC_DM_MASK 0x7 - -#define IOAPIC_VECTOR_MASK 0xff - -#define IOAPIC_IOREGSEL 0x00 -#define IOAPIC_IOWIN 0x10 -#define IOAPIC_EOI 0x40 - -#define IOAPIC_REG_ID 0x00 -#define IOAPIC_REG_VER 0x01 -#define IOAPIC_REG_ARB 0x02 -#define IOAPIC_REG_REDTBL_BASE 0x10 -#define IOAPIC_ID 0x00 - -#define IOAPIC_ID_SHIFT 24 -#define IOAPIC_ID_MASK 0xf - -#define IOAPIC_VER_ENTRIES_SHIFT 16 - - -#define TYPE_IOAPIC_COMMON "ioapic-common" -OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON) - -struct IOAPICCommonClass { - SysBusDeviceClass parent_class; - - DeviceRealize realize; - DeviceUnrealize unrealize; - void (*pre_save)(IOAPICCommonState *s); - void (*post_load)(IOAPICCommonState *s); -}; - -struct IOAPICCommonState { - SysBusDevice busdev; - MemoryRegion io_memory; - uint8_t id; - uint8_t ioregsel; - uint32_t irr; - uint64_t ioredtbl[IOAPIC_NUM_PINS]; - Notifier machine_done; - uint8_t version; - uint64_t irq_count[IOAPIC_NUM_PINS]; - int irq_level[IOAPIC_NUM_PINS]; - int irq_eoi[IOAPIC_NUM_PINS]; - QEMUTimer *delayed_ioapic_service_timer; -}; - -void ioapic_reset_common(DeviceState *dev); - -void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level); - -#endif /* QEMU_IOAPIC_INTERNAL_H */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 66e3d059ef..467311007e 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -291,12 +291,15 @@ extern const size_t pc_compat_1_5_len; extern GlobalProperty pc_compat_1_4[]; extern const size_t pc_compat_1_4_len; +int pc_machine_kvm_type(MachineState *machine, const char *vm_type); + #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ { \ MachineClass *mc = MACHINE_CLASS(oc); \ optsfn(mc); \ mc->init = initfn; \ + mc->kvm_type = pc_machine_kvm_type; \ } \ static const TypeInfo pc_machine_type_##suffix = { \ .name = namestr TYPE_MACHINE_SUFFIX, \ diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 62fa5774f8..890dfad23e 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -20,11 +20,10 @@ #include "exec/hwaddr.h" #include "qemu/notify.h" -#include "hw/i386/topology.h" #include "hw/boards.h" #include "hw/nmi.h" +#include "hw/intc/ioapic.h" #include "hw/isa/isa.h" -#include "hw/i386/ioapic.h" #include "qom/object.h" struct X86MachineClass { @@ -98,8 +97,6 @@ struct X86MachineState { #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) -void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms); - uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, unsigned int cpu_index); @@ -134,7 +131,6 @@ bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); /* Global System Interrupts */ -#define GSI_NUM_PINS IOAPIC_NUM_PINS #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) typedef struct GSIState { |