diff options
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/fsl-imx6.h | 6 | ||||
| -rw-r--r-- | include/hw/net/imx_fec.h | 250 | ||||
| -rw-r--r-- | include/hw/pci/msix.h | 1 | ||||
| -rw-r--r-- | include/hw/pci/pci.h | 11 | ||||
| -rw-r--r-- | include/hw/pci/pci_regs.h | 2 | ||||
| -rw-r--r-- | include/hw/pci/pcie.h | 5 | ||||
| -rw-r--r-- | include/hw/pci/pcie_regs.h | 5 |
7 files changed, 221 insertions, 59 deletions
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index e9157ea4b3..ec6c509d74 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -28,6 +28,7 @@ #include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/net/imx_fec.h" #include "exec/memory.h" #include "cpu.h" @@ -58,6 +59,7 @@ typedef struct FslIMX6State { IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; + IMXFECState eth; MemoryRegion rom; MemoryRegion caam; MemoryRegion ocram; @@ -436,8 +438,8 @@ typedef struct FslIMX6State { #define FSL_IMX6_HDMI_MASTER_IRQ 115 #define FSL_IMX6_HDMI_CEC_IRQ 116 #define FSL_IMX6_MLB150_LOW_IRQ 117 -#define FSL_IMX6_ENET_MAC_IRQ 118 -#define FSL_IMX6_ENET_MAC_1588_IRQ 119 +#define FSL_IMX6_ENET_MAC_1588_IRQ 118 +#define FSL_IMX6_ENET_MAC_IRQ 119 #define FSL_IMX6_PCIE1_IRQ 120 #define FSL_IMX6_PCIE2_IRQ 121 #define FSL_IMX6_PCIE3_IRQ 122 diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index cbf86509e8..62ad473b05 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -1,5 +1,5 @@ /* - * i.MX Fast Ethernet Controller emulation. + * i.MX FEC/ENET Ethernet Controller emulation. * * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> * @@ -27,27 +27,147 @@ #define TYPE_IMX_FEC "imx.fec" #define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC) +#define TYPE_IMX_ENET "imx.enet" + #include "hw/sysbus.h" #include "net/net.h" -#define FEC_MAX_FRAME_SIZE 2032 - -#define FEC_INT_HB (1 << 31) -#define FEC_INT_BABR (1 << 30) -#define FEC_INT_BABT (1 << 29) -#define FEC_INT_GRA (1 << 28) -#define FEC_INT_TXF (1 << 27) -#define FEC_INT_TXB (1 << 26) -#define FEC_INT_RXF (1 << 25) -#define FEC_INT_RXB (1 << 24) -#define FEC_INT_MII (1 << 23) -#define FEC_INT_EBERR (1 << 22) -#define FEC_INT_LC (1 << 21) -#define FEC_INT_RL (1 << 20) -#define FEC_INT_UN (1 << 19) - -#define FEC_EN 2 -#define FEC_RESET 1 +#define ENET_EIR 1 +#define ENET_EIMR 2 +#define ENET_RDAR 4 +#define ENET_TDAR 5 +#define ENET_ECR 9 +#define ENET_MMFR 16 +#define ENET_MSCR 17 +#define ENET_MIBC 25 +#define ENET_RCR 33 +#define ENET_TCR 49 +#define ENET_PALR 57 +#define ENET_PAUR 58 +#define ENET_OPD 59 +#define ENET_IAUR 70 +#define ENET_IALR 71 +#define ENET_GAUR 72 +#define ENET_GALR 73 +#define ENET_TFWR 81 +#define ENET_FRBR 83 +#define ENET_FRSR 84 +#define ENET_RDSR 96 +#define ENET_TDSR 97 +#define ENET_MRBR 98 +#define ENET_RSFL 100 +#define ENET_RSEM 101 +#define ENET_RAEM 102 +#define ENET_RAFL 103 +#define ENET_TSEM 104 +#define ENET_TAEM 105 +#define ENET_TAFL 106 +#define ENET_TIPG 107 +#define ENET_FTRL 108 +#define ENET_TACC 112 +#define ENET_RACC 113 +#define ENET_MIIGSK_CFGR 192 +#define ENET_MIIGSK_ENR 194 +#define ENET_ATCR 256 +#define ENET_ATVR 257 +#define ENET_ATOFF 258 +#define ENET_ATPER 259 +#define ENET_ATCOR 260 +#define ENET_ATINC 261 +#define ENET_ATSTMP 262 +#define ENET_TGSR 385 +#define ENET_TCSR0 386 +#define ENET_TCCR0 387 +#define ENET_TCSR1 388 +#define ENET_TCCR1 389 +#define ENET_TCSR2 390 +#define ENET_TCCR2 391 +#define ENET_TCSR3 392 +#define ENET_TCCR3 393 +#define ENET_MAX 400 + +#define ENET_MAX_FRAME_SIZE 2032 + +/* EIR and EIMR */ +#define ENET_INT_HB (1 << 31) +#define ENET_INT_BABR (1 << 30) +#define ENET_INT_BABT (1 << 29) +#define ENET_INT_GRA (1 << 28) +#define ENET_INT_TXF (1 << 27) +#define ENET_INT_TXB (1 << 26) +#define ENET_INT_RXF (1 << 25) +#define ENET_INT_RXB (1 << 24) +#define ENET_INT_MII (1 << 23) +#define ENET_INT_EBERR (1 << 22) +#define ENET_INT_LC (1 << 21) +#define ENET_INT_RL (1 << 20) +#define ENET_INT_UN (1 << 19) +#define ENET_INT_PLR (1 << 18) +#define ENET_INT_WAKEUP (1 << 17) +#define ENET_INT_TS_AVAIL (1 << 16) +#define ENET_INT_TS_TIMER (1 << 15) + +#define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ + ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ + ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ + ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ + ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ + ENET_INT_TS_AVAIL) + +/* RDAR */ +#define ENET_RDAR_RDAR (1 << 24) + +/* TDAR */ +#define ENET_TDAR_TDAR (1 << 24) + +/* ECR */ +#define ENET_ECR_RESET (1 << 0) +#define ENET_ECR_ETHEREN (1 << 1) +#define ENET_ECR_MAGICEN (1 << 2) +#define ENET_ECR_SLEEP (1 << 3) +#define ENET_ECR_EN1588 (1 << 4) +#define ENET_ECR_SPEED (1 << 5) +#define ENET_ECR_DBGEN (1 << 6) +#define ENET_ECR_STOPEN (1 << 7) +#define ENET_ECR_DSBWP (1 << 8) + +/* MIBC */ +#define ENET_MIBC_MIB_DIS (1 << 31) +#define ENET_MIBC_MIB_IDLE (1 << 30) +#define ENET_MIBC_MIB_CLEAR (1 << 29) + +/* RCR */ +#define ENET_RCR_LOOP (1 << 0) +#define ENET_RCR_DRT (1 << 1) +#define ENET_RCR_MII_MODE (1 << 2) +#define ENET_RCR_PROM (1 << 3) +#define ENET_RCR_BC_REJ (1 << 4) +#define ENET_RCR_FCE (1 << 5) +#define ENET_RCR_RGMII_EN (1 << 6) +#define ENET_RCR_RMII_MODE (1 << 8) +#define ENET_RCR_RMII_10T (1 << 9) +#define ENET_RCR_PADEN (1 << 12) +#define ENET_RCR_PAUFWD (1 << 13) +#define ENET_RCR_CRCFWD (1 << 14) +#define ENET_RCR_CFEN (1 << 15) +#define ENET_RCR_MAX_FL_SHIFT (16) +#define ENET_RCR_MAX_FL_LENGTH (14) +#define ENET_RCR_NLC (1 << 30) +#define ENET_RCR_GRS (1 << 31) + +/* TCR */ +#define ENET_TCR_GTS (1 << 0) +#define ENET_TCR_FDEN (1 << 2) +#define ENET_TCR_TFC_PAUSE (1 << 3) +#define ENET_TCR_RFC_PAUSE (1 << 4) +#define ENET_TCR_ADDSEL_SHIFT (5) +#define ENET_TCR_ADDSEL_LENGTH (3) +#define ENET_TCR_CRCFWD (1 << 9) + +/* RDSR */ +#define ENET_TWFR_TFWR_SHIFT (0) +#define ENET_TWFR_TFWR_LENGTH (6) +#define ENET_TWFR_STRFWD (1 << 8) /* Buffer Descriptor. */ typedef struct { @@ -56,22 +176,60 @@ typedef struct { uint32_t data; } IMXFECBufDesc; -#define FEC_BD_R (1 << 15) -#define FEC_BD_E (1 << 15) -#define FEC_BD_O1 (1 << 14) -#define FEC_BD_W (1 << 13) -#define FEC_BD_O2 (1 << 12) -#define FEC_BD_L (1 << 11) -#define FEC_BD_TC (1 << 10) -#define FEC_BD_ABC (1 << 9) -#define FEC_BD_M (1 << 8) -#define FEC_BD_BC (1 << 7) -#define FEC_BD_MC (1 << 6) -#define FEC_BD_LG (1 << 5) -#define FEC_BD_NO (1 << 4) -#define FEC_BD_CR (1 << 2) -#define FEC_BD_OV (1 << 1) -#define FEC_BD_TR (1 << 0) +#define ENET_BD_R (1 << 15) +#define ENET_BD_E (1 << 15) +#define ENET_BD_O1 (1 << 14) +#define ENET_BD_W (1 << 13) +#define ENET_BD_O2 (1 << 12) +#define ENET_BD_L (1 << 11) +#define ENET_BD_TC (1 << 10) +#define ENET_BD_ABC (1 << 9) +#define ENET_BD_M (1 << 8) +#define ENET_BD_BC (1 << 7) +#define ENET_BD_MC (1 << 6) +#define ENET_BD_LG (1 << 5) +#define ENET_BD_NO (1 << 4) +#define ENET_BD_CR (1 << 2) +#define ENET_BD_OV (1 << 1) +#define ENET_BD_TR (1 << 0) + +typedef struct { + uint16_t length; + uint16_t flags; + uint32_t data; + uint16_t status; + uint16_t option; + uint16_t checksum; + uint16_t head_proto; + uint32_t last_buffer; + uint32_t timestamp; + uint32_t reserved[2]; +} IMXENETBufDesc; + +#define ENET_BD_ME (1 << 15) +#define ENET_BD_TX_INT (1 << 14) +#define ENET_BD_TS (1 << 13) +#define ENET_BD_PINS (1 << 12) +#define ENET_BD_IINS (1 << 11) +#define ENET_BD_PE (1 << 10) +#define ENET_BD_CE (1 << 9) +#define ENET_BD_UC (1 << 8) +#define ENET_BD_RX_INT (1 << 7) + +#define ENET_BD_TXE (1 << 15) +#define ENET_BD_UE (1 << 13) +#define ENET_BD_EE (1 << 12) +#define ENET_BD_FE (1 << 11) +#define ENET_BD_LCE (1 << 10) +#define ENET_BD_OE (1 << 9) +#define ENET_BD_TSE (1 << 8) +#define ENET_BD_ICE (1 << 5) +#define ENET_BD_PCR (1 << 4) +#define ENET_BD_VLAN (1 << 2) +#define ENET_BD_IPV6 (1 << 1) +#define ENET_BD_FRAG (1 << 0) + +#define ENET_BD_BDU (1 << 31) typedef struct IMXFECState { /*< private >*/ @@ -80,34 +238,20 @@ typedef struct IMXFECState { /*< public >*/ NICState *nic; NICConf conf; - qemu_irq irq; + qemu_irq irq[2]; MemoryRegion iomem; - uint32_t irq_state; - uint32_t eir; - uint32_t eimr; - uint32_t rx_enabled; + uint32_t regs[ENET_MAX]; uint32_t rx_descriptor; uint32_t tx_descriptor; - uint32_t ecr; - uint32_t mmfr; - uint32_t mscr; - uint32_t mibc; - uint32_t rcr; - uint32_t tcr; - uint32_t tfwr; - uint32_t frsr; - uint32_t erdsr; - uint32_t etdsr; - uint32_t emrbr; - uint32_t miigsk_cfgr; - uint32_t miigsk_enr; uint32_t phy_status; uint32_t phy_control; uint32_t phy_advertise; uint32_t phy_int; uint32_t phy_int_mask; + + bool is_fec; } IMXFECState; #endif diff --git a/include/hw/pci/msix.h b/include/hw/pci/msix.h index 72e5f931c5..048a29dd2f 100644 --- a/include/hw/pci/msix.h +++ b/include/hw/pci/msix.h @@ -29,6 +29,7 @@ int msix_present(PCIDevice *dev); bool msix_is_masked(PCIDevice *dev, unsigned vector); void msix_set_pending(PCIDevice *dev, unsigned vector); +void msix_clr_pending(PCIDevice *dev, int vector); int msix_vector_use(PCIDevice *dev, unsigned vector); void msix_vector_unuse(PCIDevice *dev, unsigned vector); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index ef6ba51f6c..4420f47598 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -465,16 +465,23 @@ pci_get_long(const uint8_t *config) return ldl_le_p(config); } +/* + * PCI capabilities and/or their fields + * are generally DWORD aligned only so + * mechanism used by pci_set/get_quad() + * must be tolerant to unaligned pointers + * + */ static inline void pci_set_quad(uint8_t *config, uint64_t val) { - cpu_to_le64w((uint64_t *)config, val); + stq_le_p(config, val); } static inline uint64_t pci_get_quad(const uint8_t *config) { - return le64_to_cpup((const uint64_t *)config); + return ldq_le_p(config); } static inline void diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h index ba8cbe9278..7a83142578 100644 --- a/include/hw/pci/pci_regs.h +++ b/include/hw/pci/pci_regs.h @@ -1 +1,3 @@ #include "standard-headers/linux/pci_regs.h" + +#define PCI_PM_CAP_VER_1_1 0x0002 /* PCI PM spec ver. 1.1 */ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b48a7a2c5a..056d25e53c 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -80,8 +80,12 @@ struct PCIExpressDevice { /* PCI express capability helper functions */ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port); +int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port); int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); void pcie_cap_exit(PCIDevice *dev); +int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); +void pcie_cap_v1_exit(PCIDevice *dev); uint8_t pcie_cap_get_type(const PCIDevice *dev); void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); uint8_t pcie_cap_flags_get_vector(PCIDevice *dev); @@ -115,6 +119,7 @@ void pcie_add_capability(PCIDevice *dev, uint16_t offset, uint16_t size); void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); +void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); extern const VMStateDescription vmstate_pcie_device; diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 6a28b33e69..a95522a13b 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -11,6 +11,7 @@ /* express capability */ +#define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */ #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */ #define PCI_EXT_CAP_VER_SHIFT 16 #define PCI_EXT_CAP_NEXT_SHIFT 20 @@ -26,11 +27,11 @@ (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1)) /* PCI_EXP_FLAGS */ -#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */ +#define PCI_EXP_FLAGS_VER1 1 +#define PCI_EXP_FLAGS_VER2 2 #define PCI_EXP_FLAGS_IRQ_SHIFT ctz32(PCI_EXP_FLAGS_IRQ) #define PCI_EXP_FLAGS_TYPE_SHIFT ctz32(PCI_EXP_FLAGS_TYPE) - /* PCI_EXP_LINK{CAP, STA} */ /* link speed */ #define PCI_EXP_LNK_LS_25 1 |