1 files changed, 15 insertions, 63 deletions

diff --git a/target-mips/op.c b/target-mips/op.c
index 10a9b27603..a820aad7b4 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1260,7 +1260,7 @@ void op_mtc0_entrylo0 (void)
 {
     /* Large physaddr not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
+    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
     RETURN();
 }
 
@@ -1268,7 +1268,7 @@ void op_mtc0_entrylo1 (void)
 {
     /* Large physaddr not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
+    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
     RETURN();
 }
 
@@ -1338,9 +1338,9 @@ void op_mtc0_status (void)
     uint32_t val, old;
     uint32_t mask = env->Status_rw_bitmask;
 
-    /* No reverse endianness, no MDMX/DSP, no 64bit ops,
-       no 64bit addressing implemented. */
-    val = (int32_t)T0 & mask;
+    /* No reverse endianness, no MDMX/DSP, no 64bit ops
+       implemented. */
+    val = T0 & mask;
     old = env->CP0_Status;
     if (!(val & (1 << CP0St_EXL)) &&
         !(val & (1 << CP0St_ERL)) &&
@@ -1395,7 +1395,7 @@ void op_mtc0_cause (void)
 
 void op_mtc0_epc (void)
 {
-    env->CP0_EPC = (int32_t)T0;
+    env->CP0_EPC = T0;
     RETURN();
 }
 
@@ -1424,7 +1424,7 @@ void op_mtc0_watchlo0 (void)
 {
     /* Watch exceptions for instructions, data loads, data stores
        not implemented. */
-    env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
+    env->CP0_WatchLo = (T0 & ~0x7);
     RETURN();
 }
 
@@ -1453,7 +1453,7 @@ void op_mtc0_debug (void)
 
 void op_mtc0_depc (void)
 {
-    env->CP0_DEPC = (int32_t)T0;
+    env->CP0_DEPC = T0;
     RETURN();
 }
 
@@ -1489,7 +1489,7 @@ void op_mtc0_datahi (void)
 
 void op_mtc0_errorepc (void)
 {
-    env->CP0_ErrorEPC = (int32_t)T0;
+    env->CP0_ErrorEPC = T0;
     RETURN();
 }
 
@@ -1500,6 +1500,12 @@ void op_mtc0_desave (void)
 }
 
 #ifdef TARGET_MIPS64
+void op_mtc0_xcontext (void)
+{
+    env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL);
+    RETURN();
+}
+
 void op_dmfc0_entrylo0 (void)
 {
     T0 = env->CP0_EntryLo0;
@@ -1565,60 +1571,6 @@ void op_dmfc0_errorepc (void)
     T0 = env->CP0_ErrorEPC;
     RETURN();
 }
-
-void op_dmtc0_entrylo0 (void)
-{
-    /* Large physaddr not implemented */
-    /* 1k pages not implemented */
-    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
-    RETURN();
-}
-
-void op_dmtc0_entrylo1 (void)
-{
-    /* Large physaddr not implemented */
-    /* 1k pages not implemented */
-    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
-    RETURN();
-}
-
-void op_dmtc0_context (void)
-{
-    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
-    RETURN();
-}
-
-void op_dmtc0_epc (void)
-{
-    env->CP0_EPC = T0;
-    RETURN();
-}
-
-void op_dmtc0_watchlo0 (void)
-{
-    /* Watch exceptions for instructions, data loads, data stores
-       not implemented. */
-    env->CP0_WatchLo = T0 & ~0x7;
-    RETURN();
-}
-
-void op_dmtc0_xcontext (void)
-{
-    env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
-    RETURN();
-}
-
-void op_dmtc0_depc (void)
-{
-    env->CP0_DEPC = T0;
-    RETURN();
-}
-
-void op_dmtc0_errorepc (void)
-{
-    env->CP0_ErrorEPC = T0;
-    RETURN();
-}
 #endif /* TARGET_MIPS64 */
 
 /* CP1 functions */