diff options
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a0398cdc9a..3d4dc88002 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -48,6 +48,9 @@ #define MIPS_CONFIG4 \ ((0 << CP0C4_M)) +#define MIPS_CONFIG5 \ +((0 << CP0C5_M)) + /* MMU types, the first four entries have the same layout as the CP0C0_MT field. */ enum mips_mmu_types { @@ -69,6 +72,8 @@ struct mips_def_t { int32_t CP0_Config3; int32_t CP0_Config4; int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; int32_t CP0_Config6; int32_t CP0_Config7; target_ulong CP0_LLAddr_rw_bitmask; @@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4, + .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), .CP0_Config4_rw_bitmask = 0, + .CP0_Config5 = MIPS_CONFIG5, + .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | + (1 << CP0C5_CV) | (0 << CP0C5_EVA) | + (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) | + (0 << CP0C5_NFExists), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, |