diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu-models.c | 12 | ||||
| -rw-r--r-- | target-ppc/cpu-models.h | 4 | ||||
| -rw-r--r-- | target-ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target-ppc/machine.c | 8 | ||||
| -rw-r--r-- | target-ppc/misc_helper.c | 7 | ||||
| -rw-r--r-- | target-ppc/mmu-hash64.c | 42 | ||||
| -rw-r--r-- | target-ppc/mmu-hash64.h | 3 | ||||
| -rw-r--r-- | target-ppc/mmu_helper.c | 35 | ||||
| -rw-r--r-- | target-ppc/translate.c | 5 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 10 |
10 files changed, 84 insertions, 44 deletions
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 3f18996bb0..2b560a4757 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -1124,8 +1124,8 @@ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5, "POWER5") #endif - POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P, - "POWER5+") + POWERPC_DEF("POWER5+_v0.0", CPU_POWERPC_POWER5P_v00, POWER5P, + "POWER5+ v0.0") POWERPC_DEF("POWER5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P, "POWER5+ v2.1") #if defined(TODO) @@ -1144,8 +1144,8 @@ "POWER8E v1.0") POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8, "POWER8 v1.0") - POWERPC_DEF("970", CPU_POWERPC_970, 970, - "PowerPC 970") + POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970, + "PowerPC 970 v2.2") POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970, "PowerPC 970FX v1.0 (G5)") POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970, @@ -1387,11 +1387,13 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "Dino", "POWER3" }, { "POWER3+", "631" }, { "POWER5gr", "POWER5" }, - { "POWER5gs", "POWER5+" }, + { "POWER5+", "POWER5+_v0.0" }, + { "POWER5gs", "POWER5+_v0.0" }, { "POWER7", "POWER7_v2.3" }, { "POWER7+", "POWER7+_v2.1" }, { "POWER8E", "POWER8E_v1.0" }, { "POWER8", "POWER8_v1.0" }, + { "970", "970_v2.2" }, { "970fx", "970fx_v3.1" }, { "970mp", "970mp_v1.1" }, { "Apache", "RS64" }, diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index 290a7597dc..ee693af873 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -547,7 +547,7 @@ enum { CPU_POWERPC_POWER4P = 0x00380000, /* XXX: missing 0x003A0201 */ CPU_POWERPC_POWER5 = 0x003A0203, - CPU_POWERPC_POWER5P = 0x003B0000, + CPU_POWERPC_POWER5P_v00 = 0x003B0000, CPU_POWERPC_POWER5P_v21 = 0x003B0201, CPU_POWERPC_POWER6 = 0x003E0000, CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */ @@ -561,7 +561,7 @@ enum { CPU_POWERPC_POWER8E_v10 = 0x004B0100, CPU_POWERPC_POWER8_BASE = 0x004D0000, CPU_POWERPC_POWER8_v10 = 0x004D0100, - CPU_POWERPC_970 = 0x00390202, + CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, CPU_POWERPC_970FX_v21 = 0x003C0201, diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index aae33a9237..abc3545846 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -45,6 +45,7 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif +#define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 #else /* defined (TARGET_PPC64) */ @@ -1623,6 +1624,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MD_DBRAM1 (0x32A) #define SPR_RCPU_L2U_RA3 (0x32B) #define SPR_TAR (0x32F) +#define SPR_VTB (0x351) #define SPR_440_INV0 (0x370) #define SPR_440_INV1 (0x371) #define SPR_440_INV2 (0x372) diff --git a/target-ppc/machine.c b/target-ppc/machine.c index c801b822c9..3921012063 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -159,6 +159,7 @@ static int cpu_post_load(void *opaque, int version_id) PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; + target_ulong msr; /* * We always ignore the source PVR. The user or management @@ -190,7 +191,12 @@ static int cpu_post_load(void *opaque, int version_id) /* Restore htab_base and htab_mask variables */ ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - hreg_compute_hflags(env); + + /* Mark msr bits except MSR_TGPR invalid before restoring */ + msr = env->msr; + env->msr ^= ~(1ULL << MSR_TGPR); + ppc_store_msr(env, msr); + hreg_compute_mem_idx(env); return 0; diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index a577b3afd1..6b12ca86af 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -77,8 +77,13 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, void helper_store_sdr1(CPUPPCState *env, target_ulong val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (!env->external_htab) { - ppc_store_sdr1(env, val); + if (env->spr[SPR_SDR1] != val) { + ppc_store_sdr1(env, val); + tlb_flush(CPU(cpu), 1); + } } } diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index b0278c95e1..7df6edebf2 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -350,7 +350,7 @@ uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index) void ppc_hash64_stop_access(uint64_t token) { if (kvmppc_kern_htab) { - return kvmppc_hash64_free_pteg(token); + kvmppc_hash64_free_pteg(token); } } @@ -388,6 +388,24 @@ static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash, return -1; } +static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb) +{ + uint64_t epnshift; + + /* Page size according to the SLB, which we use to generate the + * EPN for hash table lookup.. When we implement more recent MMU + * extensions this might be different from the actual page size + * encoded in the PTE */ + if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_4K) { + epnshift = TARGET_PAGE_BITS; + } else if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_64K) { + epnshift = TARGET_PAGE_BITS_64K; + } else { + epnshift = TARGET_PAGE_BITS_16M; + } + return epnshift; +} + static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, ppc_slb_t *slb, target_ulong eaddr, ppc_hash_pte64_t *pte) @@ -396,12 +414,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, hwaddr hash; uint64_t vsid, epnshift, epnmask, epn, ptem; - /* Page size according to the SLB, which we use to generate the - * EPN for hash table lookup.. When we implement more recent MMU - * extensions this might be different from the actual page size - * encoded in the PTE */ - epnshift = (slb->vsid & SLB_VSID_L) - ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; + epnshift = ppc_hash64_page_shift(slb); epnmask = ~((1ULL << epnshift) - 1); if (slb->vsid & SLB_VSID_B) { @@ -448,12 +461,14 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, target_ulong eaddr) { + hwaddr mask; + int target_page_bits; hwaddr rpn = pte.pte1 & HPTE64_R_RPN; - /* FIXME: Add support for SLLP extended page sizes */ - int target_page_bits = (slb->vsid & SLB_VSID_L) - ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; - hwaddr mask = (1ULL << target_page_bits) - 1; - + /* + * We support 4K, 64K and 16M now + */ + target_page_bits = ppc_hash64_page_shift(slb); + mask = (1ULL << target_page_bits) - 1; return (rpn & ~mask) | (eaddr & mask); } @@ -617,7 +632,8 @@ void ppc_hash64_store_hpte(CPUPPCState *env, CPUState *cs = CPU(ppc_env_get_cpu(env)); if (kvmppc_kern_htab) { - return kvmppc_hash64_write_pte(env, pte_index, pte0, pte1); + kvmppc_hash64_write_pte(env, pte_index, pte0, pte1); + return; } pte_index *= HASH_PTE_SIZE_64; diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 49e385db90..291750f3e5 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -37,6 +37,9 @@ void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index, #define SLB_VSID_C 0x0000000000000080ULL /* class */ #define SLB_VSID_LP 0x0000000000000030ULL #define SLB_VSID_ATTR 0x0000000000000FFFULL +#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) +#define SLB_VSID_4K 0x0000000000000000ULL +#define SLB_VSID_64K 0x0000000000000110ULL /* * Hash page table definitions diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 660be7f18c..527c6adca3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2036,31 +2036,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); - if (env->spr[SPR_SDR1] != value) { - env->spr[SPR_SDR1] = value; + env->spr[SPR_SDR1] = value; #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { - target_ulong htabsize = value & SDR_64_HTABSIZE; + if (env->mmu_model & POWERPC_MMU_64) { + target_ulong htabsize = value & SDR_64_HTABSIZE; - if (htabsize > 28) { - fprintf(stderr, "Invalid HTABSIZE 0x" TARGET_FMT_lx - " stored in SDR1\n", htabsize); - htabsize = 28; - } - env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1; - env->htab_base = value & SDR_64_HTABORG; - } else -#endif /* defined(TARGET_PPC64) */ - { - /* FIXME: Should check for valid HTABMASK values */ - env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF; - env->htab_base = value & SDR_32_HTABORG; + if (htabsize > 28) { + fprintf(stderr, "Invalid HTABSIZE 0x" TARGET_FMT_lx + " stored in SDR1\n", htabsize); + htabsize = 28; } - tlb_flush(CPU(cpu), 1); + env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1; + env->htab_base = value & SDR_64_HTABORG; + } else +#endif /* defined(TARGET_PPC64) */ + { + /* FIXME: Should check for valid HTABMASK values */ + env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF; + env->htab_base = value & SDR_32_HTABORG; } } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 88c18e37b3..2a78e99d83 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11214,8 +11214,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int i; cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " - TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", - env->nip, env->lr, env->ctr, cpu_read_xer(env)); + TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", + env->nip, env->lr, env->ctr, cpu_read_xer(env), + cs->cpu_index); cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index df1a62c4c6..d74f4f024d 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7819,6 +7819,15 @@ static void gen_spr_power8_ebb(CPUPPCState *env) KVM_REG_PPC_BESCR, 0x00000000); } +/* Virtual Time Base */ +static void gen_spr_vtb(CPUPPCState *env) +{ + spr_register(env, SPR_VTB, "VTB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_tbl, SPR_NOACCESS, + 0x00000000); +} + static void gen_spr_power8_fscr(CPUPPCState *env) { #if defined(CONFIG_USER_ONLY) @@ -7881,6 +7890,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_power8_pmu_sup(env); gen_spr_power8_pmu_user(env); gen_spr_power8_tm(env); + gen_spr_vtb(env); } if (version < BOOK3S_CPU_POWER8) { gen_spr_book3s_dbg(env); |