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-rw-r--r--target/riscv/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 731ea2540c..9de3f716ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -538,6 +538,10 @@ struct ArchCPU {
     const GPtrArray *decoders;
 };
 
+typedef struct RISCVCPUDef {
+    RISCVMXL misa_mxl_max;  /* max mxl for this cpu */
+} RISCVCPUDef;
+
 /**
  * RISCVCPUClass:
  * @parent_realize: The parent class' realize handler.