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authorPaolo Bonzini <pbonzini@redhat.com>2025-02-06 13:12:09 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2025-05-20 08:18:42 +0200
commit71fb3aa5ebba5ba822371f864a12dbcded08147d (patch)
tree5489f04286e8862962318c75d24b73837fe75765 /target/riscv/cpu.h
parent80b22be3820f1076d9de1b1f1646ae6b352d7675 (diff)
downloadfocaccia-qemu-71fb3aa5ebba5ba822371f864a12dbcded08147d.tar.gz
focaccia-qemu-71fb3aa5ebba5ba822371f864a12dbcded08147d.zip
target/riscv: introduce RISCVCPUDef
Start putting all the CPU definitions in a struct.  Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.

Reviewed-by: Alistair Francis <alistair23@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 731ea2540c..9de3f716ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -538,6 +538,10 @@ struct ArchCPU {
     const GPtrArray *decoders;
 };
 
+typedef struct RISCVCPUDef {
+    RISCVMXL misa_mxl_max;  /* max mxl for this cpu */
+} RISCVCPUDef;
+
 /**
  * RISCVCPUClass:
  * @parent_realize: The parent class' realize handler.