diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/alpha/fpu_helper.c | 87 | ||||
| -rw-r--r-- | target/arm/vfp_helper.c | 75 | ||||
| -rw-r--r-- | target/nios2/translate.c | 20 |
3 files changed, 43 insertions, 139 deletions
diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 3ff8bb456d..63d9e9ce39 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -453,78 +453,29 @@ uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a) static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode) { - uint64_t frac, ret = 0; - uint32_t exp, sign, exc = 0; - int shift; + float64 fa; + int64_t ret; + uint32_t exc; - sign = (a >> 63); - exp = (uint32_t)(a >> 52) & 0x7ff; - frac = a & 0xfffffffffffffull; + fa = t_to_float64(a); + ret = float64_to_int64_modulo(fa, roundmode, &FP_STATUS); - if (exp == 0) { - if (unlikely(frac != 0) && !env->fp_status.flush_inputs_to_zero) { - goto do_underflow; - } - } else if (exp == 0x7ff) { - exc = FPCR_INV; - } else { - /* Restore implicit bit. */ - frac |= 0x10000000000000ull; - - shift = exp - 1023 - 52; - if (shift >= 0) { - /* In this case the number is so large that we must shift - the fraction left. There is no rounding to do. */ - if (shift < 64) { - ret = frac << shift; - } - /* Check for overflow. Note the special case of -0x1p63. */ - if (shift >= 11 && a != 0xC3E0000000000000ull) { - exc = FPCR_IOV | FPCR_INE; - } - } else { - uint64_t round; - - /* In this case the number is smaller than the fraction as - represented by the 52 bit number. Here we must think - about rounding the result. Handle this by shifting the - fractional part of the number into the high bits of ROUND. - This will let us efficiently handle round-to-nearest. */ - shift = -shift; - if (shift < 63) { - ret = frac >> shift; - round = frac << (64 - shift); - } else { - /* The exponent is so small we shift out everything. - Leave a sticky bit for proper rounding below. */ - do_underflow: - round = 1; - } + exc = get_float_exception_flags(&FP_STATUS); + if (unlikely(exc)) { + set_float_exception_flags(0, &FP_STATUS); - if (round) { - exc = FPCR_INE; - switch (roundmode) { - case float_round_nearest_even: - if (round == (1ull << 63)) { - /* Fraction is exactly 0.5; round to even. */ - ret += (ret & 1); - } else if (round > (1ull << 63)) { - ret += 1; - } - break; - case float_round_to_zero: - break; - case float_round_up: - ret += 1 - sign; - break; - case float_round_down: - ret += sign; - break; - } + /* We need to massage the resulting exceptions. */ + if (exc & float_flag_invalid_cvti) { + /* Overflow, either normal or infinity. */ + if (float64_is_infinity(fa)) { + exc = FPCR_INV; + } else { + exc = FPCR_IOV | FPCR_INE; } - } - if (sign) { - ret = -ret; + } else if (exc & float_flag_invalid) { + exc = FPCR_INV; + } else if (exc & float_flag_inexact) { + exc = FPCR_INE; } } env->error_code = exc; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 36906db8e0..789bba36cc 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1120,68 +1120,21 @@ const FloatRoundMode arm_rmode_to_sf_map[] = { uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) { float_status *status = vstatus; - uint32_t exp, sign; - uint64_t frac; - uint32_t inexact = 1; /* !Z */ - - sign = extract64(value, 63, 1); - exp = extract64(value, 52, 11); - frac = extract64(value, 0, 52); - - if (exp == 0) { - /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ - inexact = sign; - if (frac != 0) { - if (status->flush_inputs_to_zero) { - float_raise(float_flag_input_denormal, status); - } else { - float_raise(float_flag_inexact, status); - inexact = 1; - } - } - frac = 0; - } else if (exp == 0x7ff) { - /* This operation raises Invalid for both NaN and overflow (Inf). */ - float_raise(float_flag_invalid, status); - frac = 0; + uint32_t inexact, frac; + uint32_t e_old, e_new; + + e_old = get_float_exception_flags(status); + set_float_exception_flags(0, status); + frac = float64_to_int32_modulo(value, float_round_to_zero, status); + e_new = get_float_exception_flags(status); + set_float_exception_flags(e_old | e_new, status); + + if (value == float64_chs(float64_zero)) { + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ + inexact = 1; } else { - int true_exp = exp - 1023; - int shift = true_exp - 52; - - /* Restore implicit bit. */ - frac |= 1ull << 52; - - /* Shift the fraction into place. */ - if (shift >= 0) { - /* The number is so large we must shift the fraction left. */ - if (shift >= 64) { - /* The fraction is shifted out entirely. */ - frac = 0; - } else { - frac <<= shift; - } - } else if (shift > -64) { - /* Normal case -- shift right and notice if bits shift out. */ - inexact = (frac << (64 + shift)) != 0; - frac >>= -shift; - } else { - /* The fraction is shifted out entirely. */ - frac = 0; - } - - /* Notice overflow or inexact exceptions. */ - if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { - /* Overflow, for which this operation raises invalid. */ - float_raise(float_flag_invalid, status); - inexact = 1; - } else if (inexact) { - float_raise(float_flag_inexact, status); - } - - /* Honor the sign. */ - if (sign) { - frac = -frac; - } + /* Normal inexact or overflow or NaN */ + inexact = e_new & (float_flag_inexact | float_flag_invalid); } /* Pack the result and the env->ZF representation of Z together. */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a365ad8293..4264c7ec6b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -436,19 +436,19 @@ static const Nios2Instruction i_type_instructions[] = { INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_GE), /* cmpgei */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhu */ + INSTRUCTION_FLG(gen_ldx, MO_TEUW), /* ldhu */ INSTRUCTION(andi), /* andi */ - INSTRUCTION_FLG(gen_stx, MO_UW), /* sth */ + INSTRUCTION_FLG(gen_stx, MO_TEUW), /* sth */ INSTRUCTION_FLG(gen_bxx, TCG_COND_GE), /* bge */ - INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldh */ + INSTRUCTION_FLG(gen_ldx, MO_TESW), /* ldh */ INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_LT), /* cmplti */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), INSTRUCTION_NOP(), /* initda */ INSTRUCTION(ori), /* ori */ - INSTRUCTION_FLG(gen_stx, MO_UL), /* stw */ + INSTRUCTION_FLG(gen_stx, MO_TEUL), /* stw */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LT), /* blt */ - INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldw */ + INSTRUCTION_FLG(gen_ldx, MO_TEUL), /* ldw */ INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_NE), /* cmpnei */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), @@ -468,19 +468,19 @@ static const Nios2Instruction i_type_instructions[] = { INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_GEU), /* cmpgeui */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhuio */ + INSTRUCTION_FLG(gen_ldx, MO_TEUW), /* ldhuio */ INSTRUCTION(andhi), /* andhi */ - INSTRUCTION_FLG(gen_stx, MO_UW), /* sthio */ + INSTRUCTION_FLG(gen_stx, MO_TEUW), /* sthio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_GEU), /* bgeu */ - INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldhio */ + INSTRUCTION_FLG(gen_ldx, MO_TESW), /* ldhio */ INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_LTU), /* cmpltui */ INSTRUCTION_ILLEGAL(), INSTRUCTION_UNIMPLEMENTED(), /* custom */ INSTRUCTION_NOP(), /* initd */ INSTRUCTION(orhi), /* orhi */ - INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ + INSTRUCTION_FLG(gen_stx, MO_TESL), /* stwio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ - INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ + INSTRUCTION_FLG(gen_ldx, MO_TEUL), /* ldwio */ INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ |