summary refs log tree commit diff stats
Commit message (Collapse)AuthorAgeFilesLines
* qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffixPhilippe Mathieu-Daudé2025-03-083-2/+2
| | | | | | | | | | | | | | | | | | | Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'atomic128-cas.h' as 'atomic128-cas.h.inc'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241212141018.59428-2-philmd@linaro.org>
* accel/tcg: Split out getpc.hRichard Henderson2025-03-082-9/+25
| | | | | | | | | | Split out GETPC to a target-independent header. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250308072348.65723-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h'Philippe Mathieu-Daudé2025-03-082-9/+11
| | | | | | | | | GETPC_ADJ is only used within accel/tcg/, no need to expose it to all the code base. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250308072348.65723-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Build tcg-accel-ops-mttcg.c onceRichard Henderson2025-03-082-2/+1
| | | | | | | All that is required is to avoid including exec-all.h. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Build tcg-accel-ops-rr.c onceRichard Henderson2025-03-082-2/+2
| | | | | | | All that is required is to use cpu-common.h instead of exec-all.h. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Build tcg-accel-ops-icount.c onceRichard Henderson2025-03-082-2/+2
| | | | | | | All that is required is to avoid including exec-all.h. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Build tcg-accel-ops.c onceRichard Henderson2025-03-081-1/+1
| | | | | | | | Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h, it can be built once. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* system: Build watchpoint.c onceRichard Henderson2025-03-081-1/+1
| | | | | | | | | | Now that watchpoint.c uses cputlb.h instead of exec-all.h, it can be built once. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Declare tlb_flush*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-0834-211/+224
| | | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Declare tlb_hit*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-082-23/+23
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-20-philmd@linaro.org>
* exec: Declare tlb_set_page() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-0815-15/+24
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-18-philmd@linaro.org>
* exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-084-27/+30
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-17-philmd@linaro.org>
* exec: Declare tlb_set_page_full() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-083-23/+24
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-16-philmd@linaro.org>
* exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-084-3/+9
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Compile watchpoint.c onceRichard Henderson2025-03-084-6/+5
| | | | | | | | | | | | Move tb_check_watchpoint declaration from tb-internal.h, which is still target-specific, to internal-common.h, which isn't. Otherwise, all that is required to build watchpoint.c once is to include the new exec/cpu-interrupt.h instead of exec/exec-all.h. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Split out exec/cpu-interrupt.hRichard Henderson2025-03-083-65/+71
| | | | | | | | | | | | Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Move TARGET_PAGE_{SIZE,MASK,BITS} to target_page.hRichard Henderson2025-03-075-48/+51
| | | | | | | | | Re-use the TARGET_PAGE_BITS_VARY mechanism to define TARGET_PAGE_SIZE and friends when not compiling per-target. Inline qemu_target_page_{size,mask,bits} as they are now trivial. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/Philippe Mathieu-Daudé2025-03-072-26/+27
| | | | | | | | | | CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250305191859.71608-1-philmd@linaro.org>
* linux-user/main: Allow setting tb-sizeIlya Leoshkevich2025-03-071-0/+12
| | | | | | | | | | | While qemu-system can set tb-size using -accel tcg,tb-size=n, there is no similar knob for qemu-user. Add one in a way similar to how one-insn-per-tb is already handled. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240730215532.1442-1-iii@linux.ibm.com>
* Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-03-07110-535/+546
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic CPUs / accelerators patch queue - Merge "qemu/clang-tsa.h" within "qemu/compiler.h" - Various cleanups around accelerators initialization code (better user/system split) - Various trivial cleanups in accel/tcg/, Guard few TCG calls with tcg_enabled() - Explicit disassemble_info endianness - Improve dual-endianness support for MicroBlaze # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfJw08ACgkQ4+MsLN6t # wN70whAAtfcdWtqseFfb6fvDtjflgxN51Ui0iaOECXUA18USKriGy34eBcMYMiM2 # +eKgU7+jI6JGE4+burcgWUsPpFFF951/A8+lyIbFgO5yToTDmC+qNe4XfmMAIyXq # uf9Obr2c0Xk9luh4odb+jPAQodw/7G1fKgcCVIJNDCl/xEcPhS9eNpTaHwcVnkWI # K6KrxWXOsqG6+evJBPWYoXtOOyt0+JcwAsJoGhprwtGm3P9+jSVXsgeGsJVyZcna # f32JtjWL754O8XeMkOn4x6rt58VrCIMKI9xT7keDyuhTCq0Zki9RO2nMU2dSw5mN # AfL9hxqUy0Nijnyslg3ugujDfTePsNyLdwwH7n0mnoD72ELi6WnhDsmOThuEB3Rd # 4/kdwTJfA/rlWk/GF1tbKW7AvQZokRARtzmL3V0HmGJu57lX+2JuszEdYBkqDEP7 # GH1I10B2yANUm+C9y3X8qWOU7Ws433ebJeJoZuyfnbZ9Me+UfRmql/oS+V8ata2i # fArEItpldUFrWRyYLkTbXrh2dgyV9yJTEir/lzOzeAZZzyabTbjf2z9qnh976GGO # 1QnDy5QA4f54kDBUZe7JK26TZsHPch7cgqXW6f8tRlJF7A9hxGK8d2TUV/lC3/vx # LUOlWNu03PhiruYmZEcWOsY3Jt9jRCF6lIryrnaJsqnVOVmMUMM= # =3TRh # -----END PGP SIGNATURE----- # gpg: Signature made Thu 06 Mar 2025 23:46:23 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-cpus-20250306' of https://github.com/philmd/qemu: (54 commits) include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition system: Open-code qemu_init_arch_modules() using target_name() target/i386: Mark WHPX APIC region as little-endian target/alpha: Do not mix exception flags and FPCR bits target/riscv: Convert misa_mxl_max using GLib macros target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL target/xtensa: Finalize config in xtensa_register_core() target/sparc: Constify SPARCCPUClass::cpu_def target/i386: Constify X86CPUModel uses disas: Remove target_words_bigendian() call in initialize_debug_target() target/xtensa: Set disassemble_info::endian value in disas_set_info() target/sh4: Set disassemble_info::endian value in disas_set_info() target/riscv: Set disassemble_info::endian value in disas_set_info() target/ppc: Set disassemble_info::endian value in disas_set_info() target/mips: Set disassemble_info::endian value in disas_set_info() target/microblaze: Set disassemble_info::endian value in disas_set_info target/arm: Set disassemble_info::endian value in disas_set_info() target: Set disassemble_info::endian value for big-endian targets target: Set disassemble_info::endian value for little-endian targets target/mips: Fix possible MSA int overflow ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * include: Poison TARGET_PHYS_ADDR_SPACE_BITS definitionPhilippe Mathieu-Daudé2025-03-061-0/+1
| | | | | | | | | | | | | | | | Ensure common code never use this target specific definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305153929.43687-4-philmd@linaro.org>
| * system: Open-code qemu_init_arch_modules() using target_name()Philippe Mathieu-Daudé2025-03-063-12/+6
| | | | | | | | | | | | | | | | | | | | Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules") but using target_name() instead of the target specific 'TARGET_NAME' definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305005225.95051-3-philmd@linaro.org>
| * target/i386: Mark WHPX APIC region as little-endianPhilippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-6-philmd@linaro.org>
| * target/alpha: Do not mix exception flags and FPCR bitsPhilippe Mathieu-Daudé2025-03-061-8/+7
| | | | | | | | | | | | | | | | | | get_float_exception_flags() returns exception flags, which are distinct from the FPCR bits used as error code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250211162604.83446-1-philmd@linaro.org>
| * target/riscv: Convert misa_mxl_max using GLib macrosPhilippe Mathieu-Daudé2025-03-061-5/+5
| | | | | | | | | | | | | | | | | | Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-6-philmd@linaro.org>
| * target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXLPhilippe Mathieu-Daudé2025-03-062-2/+2
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-5-philmd@linaro.org>
| * target/xtensa: Finalize config in xtensa_register_core()Philippe Mathieu-Daudé2025-03-062-3/+4
| | | | | | | | | | | | | | | | | | | | | | Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20250210133134.90879-4-philmd@linaro.org>
| * target/sparc: Constify SPARCCPUClass::cpu_defPhilippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-3-philmd@linaro.org>
| * target/i386: Constify X86CPUModel usesPhilippe Mathieu-Daudé2025-03-062-5/+5
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-2-philmd@linaro.org>
| * disas: Remove target_words_bigendian() call in initialize_debug_target()Philippe Mathieu-Daudé2025-03-061-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All CPUClass implementating disas_set_info() must set the disassemble_info::endian value. Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before calling the CPUClass::disas_set_info() handler, then asserting %endian is not BFD_ENDIAN_UNKNOWN after the call. This allows removing the target_words_bigendian() call in disas/. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250210212931.62401-11-philmd@linaro.org>
| * target/xtensa: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-10-philmd@linaro.org>
| * target/sh4: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-9-philmd@linaro.org>
| * target/riscv: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-0/+9
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-8-philmd@linaro.org>
| * target/ppc: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback always set\ the disassemble_info::endian field. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-7-philmd@linaro.org>
| * target/mips: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-5/+5
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-6-philmd@linaro.org>
| * target/microblaze: Set disassemble_info::endian value in disas_set_infoPhilippe Mathieu-Daudé2025-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-5-philmd@linaro.org>
| * target/arm: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé2025-03-061-7/+3
| | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-4-philmd@linaro.org>
| * target: Set disassemble_info::endian value for big-endian targetsPhilippe Mathieu-Daudé2025-03-065-0/+5
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-3-philmd@linaro.org>
| * target: Set disassemble_info::endian value for little-endian targetsPhilippe Mathieu-Daudé2025-03-066-0/+6
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for little-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-2-philmd@linaro.org>
| * target/mips: Fix possible MSA int overflowDenis Rastyogin2025-03-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df) is 64 by using a 64-bit integer for the shift operation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reported-by: Dmitriy Fedin <d.fedin@fobos-nt.ru> Signed-off-by: Denis Rastyogin <gerben@altlinux.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20250124122707.54264-1-gerben@altlinux.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * target/tricore: Ensure not being build on user emulationPhilippe Mathieu-Daudé2025-03-061-0/+4
| | | | | | | | | | | | | | | | | | Currently only system emulation is supported. Assert no target code is built for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-4-philmd@linaro.org>
| * target/rx: Ensure not being build on user emulationPhilippe Mathieu-Daudé2025-03-063-12/+4
| | | | | | | | | | | | | | | | | | | | | | Currently only system emulation is supported. Assert no target code is built for user emulation. Remove #ifdef'ry since more work is required before being able to emulate a user process. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-3-philmd@linaro.org>
| * target/hexagon: Ensure not being build on system emulationPhilippe Mathieu-Daudé2025-03-061-0/+4
| | | | | | | | | | | | | | | | | | Currently only user emulation is supported. Assert no target code is built for system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Message-Id: <20250121142341.17001-2-philmd@linaro.org>
| * target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize()Philippe Mathieu-Daudé2025-03-063-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | OpenRISC timer is architecturally tied to the CPU. It doesn't belong to the machine init() code to instanciate it: move its creation when a vCPU is realized (after being created). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250114231304.77150-1-philmd@linaro.org>
| * target/i386/hvf: Variable type fixup in decoderPhil Dennis-Jordan2025-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241209203629.74436-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * target/microblaze: Consider endianness while translating codePhilippe Mathieu-Daudé2025-03-062-2/+10
| | | | | | | | | | | | | | | | | | Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-17-philmd@linaro.org>
| * target/microblaze: Introduce mo_endian() helperPhilippe Mathieu-Daudé2025-03-061-4/+10
| | | | | | | | | | | | | | | | mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-16-philmd@linaro.org>
| * target/microblaze: Set MO_TE once in do_load() / do_store()Philippe Mathieu-Daudé2025-03-061-16/+20
| | | | | | | | | | | | | | | | | | All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-15-philmd@linaro.org>
| * target/microblaze: Explode MO_TExx -> MO_TE | MO_xxPhilippe Mathieu-Daudé2025-03-061-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20241105130431.22564-14-philmd@linaro.org>
| * hw/core/generic-loader: Do not open-code cpu_set_pc()Philippe Mathieu-Daudé2025-03-061-4/+1
| | | | | | | | | | | | | | | | Directly call cpu_set_pc() instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250122093028.52416-2-philmd@linaro.org>