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| * block: Parse 'detect-zeroes' in bdrv_open_common()Kevin Wolf2016-09-292-8/+34
| | | | | | | | | | | | | | | | | | | | Amongst others, this means that you can now use the 'detect-zeroes' option for non-top-level nodes in blockdev-add, like the QAPI schema promises. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
| * block/qapi: Move 'aio' option to file driverKevin Wolf2016-09-294-27/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The option whether or not to use a native AIO interface really isn't a generic option for all drivers, but only applies to the native file protocols. This patch moves the option in blockdev-add to the appropriate places (raw-posix and raw-win32). We still have to keep the flag BDRV_O_NATIVE_AIO for compatibility because so far the AIO option was usually specified on the wrong layer (the top-level format driver, which didn't even look at it) and then inherited by the protocol driver (where it was actually used). We can't forbid this use except in new interfaces. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
| * block/qapi: Use separate options type for curl driverKevin Wolf2016-09-291-7/+18
| | | | | | | | | | | | | | | | | | We're going to add an option to the file drivers which doesn't apply to the curl drivers, so give them a separate option type. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
| * block: Drop aio/cache consistency check from qmp_blockdev_add()Kevin Wolf2016-09-292-16/+1
| | | | | | | | | | | | | | | | | | | | The TODO comment has been addressed a while ago and this is now checked in raw-posix, so we don't have to special case this in blockdev-add any more. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
| * block: Fix error path in qmp_blockdev_change_medium()Kevin Wolf2016-09-291-1/+1
| | | | | | | | | | | | | | | | Commit 00949bab incorrectly changed one instance of &err into errp while touching the line. Change it back. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
| * block-backend: remove blk_flush_allJohn Snow2016-09-294-25/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can teach Xen to drain and flush each device as it needs to, instead of trying to flush ALL devices. This removes the last user of blk_flush_all. The function is therefore removed under the premise that any new uses of blk_flush_all would be the wrong paradigm: either flush the single device that requires flushing, or use an appropriate flush_all mechanism from outside of the BlkBackend layer. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Acked-by: Fam Zheng <famz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * qemu: use bdrv_flush_all for vm_stop et alJohn Snow2016-09-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reimplement bdrv_flush_all for vm_stop. In contrast to blk_flush_all, bdrv_flush_all does not have device model restrictions. This allows us to flush and halt unconditionally without error. This allows us to do things like migrate when we have a device with an open tray, but has a node that may need to be flushed, or nodes that aren't currently attached to any device and need to be flushed. Specifically, this allows us to migrate when we have a CDROM with an open tray. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Acked-by: Fam Zheng <famz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * block: reintroduce bdrv_flush_allJohn Snow2016-09-292-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fe1a9cbc moved the flush_all routine from the bdrv layer to the block-backend layer. In doing so, however, the semantics of the routine changed slightly such that flush_all now used blk_flush instead of bdrv_flush. blk_flush can fail if the attached device model reports that it is not "available," (i.e. the tray is open.) This changed the semantics of flush_all such that it can now fail for e.g. open CDROM drives. Reintroduce bdrv_flush_all to regain the old semantics without having to alter the behavior of blk_flush or blk_flush_all, which are already 'doing the right thing.' Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Acked-by: Fam Zheng <famz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2016-10-0439-316/+2027
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20161004' into staging target-arm queue: * Netduino 2 improvements (SPI, ADC devices) * fix some Mainstone key mappings * vmstateify tsc210x, tsc2005 * virt: add 2.8 machine type * virt: support in-kernel GICv3 ITS * generic-loader device * A64: fix iss_sf decoding in disas_ld_lit * correctly handle 'sub pc, pc, 1' for ARMv6 # gpg: Signature made Tue 04 Oct 2016 13:41:34 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits) target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 target-arm: A64: Fix decoding of iss_sf in disas_ld_lit cadence_gem: Fix priority queue out of bounds access docs: Add a generic loader explanation document generic-loader: Add a generic loader ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table ACPI: Add GIC Interrupt Translation Service Structure definition arm/virt: Add ITS to the virt board hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation kvm-all: Pass requester ID to MSI routing functions target-arm: move gicv3_class_name from machine to kvm_arm.h hw/intc/arm_gicv3_its: Implement ITS base class hw/intc/arm_gic(v3)_kvm: Initialize gsi routing hw/arm/virt: add 2.8 machine type vmstateify tsc210x vmstateify tsc2005 hw/arm: Fix Integrator/CM initialization mainstone: Add mapping for dot, slash and backspace. mainstone: Fix incorrect key mapping for Enter key. MAINTAINERS: Add Alistair to the maintainers list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6Peter Maydell2016-10-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking branch, so the computed new value is written to r15 as a normal value. The architecture says that in this case, bits [1:0] of the value written must be ignored if we are in ARM mode (or bit [0] ignored if in Thumb mode); this is a change from the ARMv4/v5 specification that behaviour is UNPREDICTABLE. Use the correct mask on the PC value when doing a non-interworking store to PC. A popular library used on RaspberryPi uses this instruction as part of a trick to determine whether it is running on ARMv6 or ARMv7, and we were mishandling the sequence. Fixes bug: https://bugs.launchpad.net/bugs/1625295 Reported-by: <stu.axon@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Fix decoding of iss_sf in disas_ld_litEdgar E. Iglesias2016-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | cadence_gem: Fix priority queue out of bounds accessAlistair Francis2016-10-041-18/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was an error with some of the register implementation assuming there are 16 priority queues supported when the IP only supports 8. This patch corrects the registers to only support 8 queues. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | docs: Add a generic loader explanation documentAlistair Francis2016-10-041-0/+84
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | generic-loader: Add a generic loaderAlistair Francis2016-10-044-0/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic loader to QEMU which can be used to load images or set memory values. Internally inside QEMU this is a device. It is a strange device that provides no hardware interface but allows QEMU to monkey patch memory specified when it is created. To be able to do this it has a reset callback that does the memory operations. This device allows the user to monkey patch memory. To be able to do this it needs a backend to manage the datas, the same as other memory-related devices. In this case as the backend is so trivial we have merged it with the frontend instead of creating and maintaining a seperate backend. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT tableShannon Zhao2016-10-041-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If GIC ITS is supported, add description in ACPI MADT table, then guest could use ITS when booting with ACPI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ACPI: Add GIC Interrupt Translation Service Structure definitionShannon Zhao2016-10-041-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure. Here we add the definition of the Structure. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | arm/virt: Add ITS to the virt boardPavel Fedin2016-10-041-6/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If supported by the configuration, ITS will be added automatically. This patch also renames v2m_phandle to msi_phandle because it's now used by both MSI implementations. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulationPavel Fedin2016-10-042-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ITS control frame is in-kernel emulated while accesses to the GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI direct MSI injection advertised by the CAP_SIGNAL_MSI capability) the kvm_gsi_direct_mapping is explicitly set to false to emphasize the difference with GICv2M. Direct mapping cannot work with ITS since the content of the MSI data is not the target interrupt ID but an eventd id. GSI routing is advertised (kvm_gsi_routing_allowed) as well as msi/irqfd signaling (kvm_msi_via_irqfd_allowed). The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI ioctl. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | kvm-all: Pass requester ID to MSI routing functionsPavel Fedin2016-10-043-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce global kvm_msi_use_devid flag plus associated kvm_msi_devid_required() macro. Passes the device ID, if needed, while building the MSI route entry. Device IDs are required by the ARM GICv3 ITS (IRQ remapping function is based on this information). Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-arm: move gicv3_class_name from machine to kvm_arm.hEric Auger2016-10-042-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Machine.c contains code related to migration. Let's move gicv3_class_name to kvm_arm.h instead. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gicv3_its: Implement ITS base classPavel Fedin2016-10-044-0/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the basic skeleton for both KVM and software-emulated ITS. Since we already prepare status structure, we also introduce complete VMState description. But, because we currently have no migratable implementations, we also set unmigratable flag. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gic(v3)_kvm: Initialize gsi routingEric Auger2016-10-042-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Advertise gsi routing and set up irqchip routing entries for GIC SPIs. This is not mandated as long as MSI routing is not used (because the kernel sets a default irqchip routing table). However once MSI routing gets used (for VIRTIO-PCI vhost for example), the first call to KVM_SET_GSI_ROUTING overrides the kernel default irqchip table. If no routing entry exists for the GSI, any IRQFD signaling for this GSI will fail. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: add 2.8 machine typeAndrew Jones2016-10-041-2/+17
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1474641676-25017-1-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vmstateify tsc210xDr. David Alan Gilbert2016-10-041-123/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm now saving all 3 of the pll entries; only 2 were saved before. There are a couple of times that were previously stored as offsets from 'now' calculated before saving; with vmstate it's easier to store the 'now' and fix it up on reload. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1474977735-10156-3-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vmstateify tsc2005Dr. David Alan Gilbert2016-10-041-115/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've converted the fields in it's main data structure to fixed size types in ways that look sane. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1474977735-10156-2-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: Fix Integrator/CM initializationJakub Jermar2016-10-041-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialization of a class instance cannot depend on its own properties as these are not yet set. Move parts of integratorcm_init() that depend on the "memsz" property to the newly added integratorcm_realize(). This fixes: https://bugs.launchpad.net/qemu/+bug/1624726 Signed-off-by: Jakub Jermar <jakub@jermar.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | mainstone: Add mapping for dot, slash and backspace.Vijay Kumar B2016-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missed out mappings. These mappings are from the "Intel PXA27x Processor Developer's Kit User Guide". Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com> Reviewed-by: Deepak S. <deepak@zilogic.com> Message-id: 1475063033-8176-3-git-send-email-vijaykumar@zilogic.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | mainstone: Fix incorrect key mapping for Enter key.Vijay Kumar B2016-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the manual the (5, 5) corresponds to backspace key, and not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up to match the mapping in the Linux kernel. Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com> Reviewed-by: Deepak S. <deepak@zilogic.com> Message-id: 1475063033-8176-2-git-send-email-vijaykumar@zilogic.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | MAINTAINERS: Add Alistair to the maintainers listAlistair Francis2016-10-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Alistair Francis as the maintainer for the Netduino 2 and SMM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5a46ccf398b050a41cc3b3d0e94bcff4ce2d85e0.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F205: Connect the SPI devicesAlistair Francis2016-10-042-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Connect the SPI devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F205: Connect the ADC devicesAlistair Francis2016-10-042-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | irq: Add a new irq device that allows the ORing of linesAlistair Francis2016-10-043-0/+152
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair@alistair23.me> Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F2xx: Add the SPI deviceAlistair Francis2016-10-044-0/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the STM32F2xx SPI device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F2xx: Add the ADC deviceAlistair Francis2016-10-045-0/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F2xx: Display PWM duty cycle from timerAlistair Francis2016-10-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cdb59039a25e061615713a94b40797baa12ea9f9.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | STM32F205: Remove the individual device variablesAlistair Francis2016-10-041-18/+17
|/ / | | | | | | | | | | | | | | | | | | | | Cleanup the individual DeviceState and SysBusDevice variables to re-use the same variable for each device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fc5d75a57d320b69704df2c1146ff0fd482e4a88.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell2016-10-042-11/+29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging x86 bug fixes Fix for a XSAVE regression when using "-cpu host", and a fix on the Opteron_G3 CPU model. # gpg: Signature made Mon 03 Oct 2016 20:08:13 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: target-i386: Correct family/model/stepping for Opteron_G3 target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-i386: Correct family/model/stepping for Opteron_G3Evgeny Yakovlev2016-10-032-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current CPU definition for AMD Opteron third generation includes features like SSE4a and LAHF_LM support in emulated CPUID. These features are present in K8 rev.E or K10 CPUs and later. However, current G3 family and model describe 2nd generation K8 cores instead. This is incorrect but was considered harmless until our tests found a problem with linux kernels >= 3.10 (and maybe earlier) which specifically check for Opteron K8 model when parsing CPUID leaf 0x80000001: http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c?v=3.16#L552 This code will disable LAHF_LM feature in /proc/cpuinfo if model number is inconsistent. This change sets Opteron_G3 family/model/stepping to 16/2/3 which is a proper Opteron 3rd generation 2350 CPU. Signed-off-by: Evgeny Yakovlev <eyakovlev@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * | target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratableEduardo Habkost2016-10-031-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A regression was introduced by commit 96193c22a "target-i386: Move xsave component mask to features array": all CPUID[EAX=0xD,ECX=0]:EAX bits were being reported as unmigratable because they don't have feature names defined. This broke "-cpu host" because it enables only migratable features by default. This adds a new field to FeatureWordInfo: migratable_flags, which will make those features be reported as migratable even if they don't have a property name defined. Reported-by: Wanpeng Li <wanpeng.li@hotmail.com> Cc: Paolo Bonzini <bonzini@gnu.org> Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | | Merge remote-tracking branch 'remotes/famz/tags/for-upstream' into stagingPeter Maydell2016-10-047-2/+13
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # gpg: Signature made Sun 02 Oct 2016 02:49:58 BST # gpg: using RSA key 0xCA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/for-upstream: docker: Build in a clean directory smbios: fix uuid copy xenpv: Fix qemu_uuid compiling error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | docker: Build in a clean directoryFam Zheng2016-10-025-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we configure and build under "$QEMU_SRC/tests/docker" which is dubious. Create a fixed directory (to be friendly to ccache) and change to there before calling build_qemu. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <1475047892-11955-1-git-send-email-famz@redhat.com>
| * | smbios: fix uuid copyMarc-André Lureau2016-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 9c5ce8db, the uuid is wrongly copied, as QemuUUID 'in' argument is already a pointer. Fixes ASAN complaining: hw/smbios/smbios.c:489:5: runtime error: load of address 0x7fffcdb91b00 with insufficient space for an object of type '__int128 unsigned' Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20160928143810.25558-1-marcandre.lureau@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [Warp the long error message line in commit message. - Fam] Signed-off-by: Fam Zheng <famz@redhat.com>
| * | xenpv: Fix qemu_uuid compiling errorFam Zheng2016-09-291-1/+1
| |/ | | | | | | | | | | | | | | | | | | 9c5ce8db2 switched the type of qemu_uuid and this should have followed. Fix it. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <1474968011-29382-1-git-send-email-famz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
* | Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into ↵Peter Maydell2016-09-307-34/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Couple of s390x patches: - some PCI cleanups - fix build error due to uuid rework - fix potential deadlock in sigp handling - enable ccw devices in BIOS and enforce checking in QEMU # gpg: Signature made Wed 28 Sep 2016 12:27:03 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20160927: s390x/kvm: fix build against qemu_uuid s390x/css: {c,h,t,r,x}sch: require enable AND device number valid pc-bios/s390-ccw.img: rebuild image pc-bios/s390-ccw: enable subchannel for IPL I/O devices s390x/kvm: Fix potential deadlock in sigp handling s390x/pci: code cleanup s390x/pci: assign msix io region for each pci device s390x/pci: re-arrange variable declarations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/kvm: fix build against qemu_uuidChristian Borntraeger2016-09-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit 9c5ce8db2e5c ("vl: Switch qemu_uuid to QemuUUID") changed most users of qemu_uuid but not all. Fix a build error on s390/kvm. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
| * | s390x/css: {c,h,t,r,x}sch: require enable AND device number validSascha Silbe2016-09-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PoP, subchannels are only considered operational if they are enabled _and_ the device number is valid. With the current checks being enabled _or_ having a valid device number was sufficient. This caused qemu to allow IO on subchannels that were not enabled. Fix the checks to require both bits to be set. Signed-off-by: Sascha Silbe <silbe@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
| * | pc-bios/s390-ccw.img: rebuild imageChristian Borntraeger2016-09-281-0/+0
| | | | | | | | | | | | | | | | | | | | | Contains: - pc-bios/s390-ccw: enable subchannel for IPL I/O devices Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
| * | pc-bios/s390-ccw: enable subchannel for IPL I/O devicesDong Jia Shi2016-09-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPL should cause the IPL I/O device to become enabled. So when handling the IPL program, we should set the E (Enable) bit. However, virtio-ccw does not know whether it's dealing with an IPL device or not. Since trying to perform I/O on a disabled device doesn't make any sense, let's just always enable it. At the same time we can remove the SCSW_FCTL_START_FUNC flag as it is ignored for msch anyway and did not enable the device as intended. Reported-by: Farhan Ali <alifm@linux.vnet.ibm.com> Signed-off-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Sascha Silbe <silbe@linux.vnet.ibm.com> Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> [remove superfluous flag] Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
| * | s390x/kvm: Fix potential deadlock in sigp handlingChristian Borntraeger2016-09-281-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If two VCPUs exit at the same time and target each other with a sigp, both could run into a deadlock as run_on_cpu on CPU0 will free the BQL when starting the CPU1 target routine. CPU1 will run its sigp initiater for CPU0 before handling the run_on_cpu requests, thus resulting in a dead lock. As all qemu SIGPs are slow path anway we can use a big sigp lock and allow only one SIGP for the guest at a time. We will return condition code 2 (BUSY) on contention to the guest. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
| * | s390x/pci: code cleanupYi Min Zhao2016-09-281-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that each S390 PCI device uses an IO region as MSIX region. The code in s390_translate_iommu() will never be triggered. Let's remove it. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>