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* migration/rdma: Fix cm event use after freeLi Zhijian2021-06-081-3/+8
| | | | | | | Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com> Message-Id: <20210602023506.3821293-1-lizhijian@cn.fujitsu.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* yank: Unregister function when using TLS migrationLeonardo Bras2021-06-083-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After yank feature was introduced in migration, whenever migration is started using TLS, the following error happens in both source and destination hosts: (qemu) qemu-kvm: ../util/yank.c:107: yank_unregister_instance: Assertion `QLIST_EMPTY(&entry->yankfns)' failed. This happens because of a missing yank_unregister_function() when using qio-channel-tls. Fix this by also allowing TYPE_QIO_CHANNEL_TLS object type to perform yank_unregister_function() in channel_close() and multifd_load_cleanup(). Also, inside migration_channel_connect() and migration_channel_process_incoming() move yank_register_function() so it only runs once on a TLS migration. Fixes: b5eea99ec2f ("migration: Add yank feature", 2021-01-13) Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1964326 Signed-off-by: Leonardo Bras <leobras.c@gmail.com> Reviewed-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Peter Xu <peterx@redhat.com> -- Changes since v2: - Dropped all references to ioc->master - yank_register_function() and yank_unregister_function() now only run once in a TLS migration. Changes since v1: - Cast p->c to QIOChannelTLS into multifd_load_cleanup() Message-Id: <20210601054030.1153249-1-leobras.c@gmail.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-06-0823-185/+1258
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging Second RISC-V PR for QEMU 6.1 - Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension # gpg: Signature made Tue 08 Jun 2021 01:28:27 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits) target/riscv: rvb: add b-ext version cpu option target/riscv: rvb: support and turn on B-extension from command line target/riscv: rvb: add/shift with prefix zero-extend target/riscv: rvb: address calculation target/riscv: rvb: generalized or-combine target/riscv: rvb: generalized reverse target/riscv: rvb: rotate (left/right) target/riscv: rvb: shift ones target/riscv: rvb: single-bit instructions target/riscv: add gen_shifti() and gen_shiftiw() helper functions target/riscv: rvb: sign-extend instructions target/riscv: rvb: min/max instructions target/riscv: rvb: pack two words into one register target/riscv: rvb: logic-with-negate target/riscv: rvb: count bits set target/riscv: rvb: count leading/trailing zeros target/riscv: reformat @sh format encoding for B-extension target/riscv: Pass the same value to oprsz and maxsz. target/riscv/pmp: Add assert for ePMP operations target/riscv: Dump CSR mscratch/sscratch/satp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-082-0/+26
| | | | | | | | | | | | | | | | | | Default b-ext version is v0.93. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-18-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-082-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-17-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-083-0/+35
| | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-16-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: address calculationKito Cheng2021-06-083-0/+62
| | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-15-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: generalized or-combineFrank Chang2021-06-085-0/+64
| | | | | | | | | | | | | | Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-14-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: generalized reverseFrank Chang2021-06-086-0/+132
| | | | | | | | | | | | | | Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-13-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-083-0/+81
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-12-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: shift onesKito Cheng2021-06-083-0/+74
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-11-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: single-bit instructionsFrank Chang2021-06-083-0/+175
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-10-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-082-50/+43
| | | | | | | | | | | | | | | | | | | | | | Add gen_shifti() and gen_shiftiw() helper functions to reuse the same interfaces for immediate shift instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-9-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-082-0/+15
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: min/max instructionsKito Cheng2021-06-082-0/+28
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: pack two words into one registerKito Cheng2021-06-083-0/+78
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: logic-with-negateKito Cheng2021-06-082-0/+21
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: count bits setFrank Chang2021-06-083-0/+21
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-084-1/+93
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: reformat @sh format encoding for B-extensionKito Cheng2021-06-081-5/+5
| | | | | | | | | | | | | | | | | | Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei2021-06-081-39/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv/pmp: Add assert for ePMP operationsAlistair Francis2021-06-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Although we construct epmp_operation in such a way that it can only be between 0 and 15 Coverity complains that we don't handle the other possible cases. To fix Coverity and make it easier for humans to read add a default case to the switch statement that calls g_assert_not_reached(). Fixes: CID 1453108 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
| * target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du2021-06-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | This dumps the CSR mscratch/sscratch/satp and meanwhile aligns the output of CSR mtval/stval. Signed-off-by: Changbin Du <changbin.du@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210519155738.20486-1-changbin.du@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-082-4/+2
| | | | | | | | | | | | | | | | | | | | | | riscv_excp_names[] and riscv_intr_names[] are only referenced by target/riscv/cpu.c locally. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | Physical Memory Protection is a system feature. Avoid polluting the user-mode emulation by its definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210516205333.696094-1-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs/system: Move the RISC-V -bios information to removedAlistair Francis2021-06-083-20/+17
| | | | | | | | | | | | | | | | | | | | | | QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt and sifive_u machines. This patch moves that change from the deprecated.rst file to the removed-features.rst file and the target-riscv.rst. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
| * target/riscv: fix wfi exception behaviorJose Martins2021-06-082-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wfi exception trigger behavior should take into account user mode, hstatus.vtw, and the fact the an wfi might raise different types of exceptions depending on various factors: If supervisor mode is not present: - an illegal instruction exception should be generated if user mode executes and wfi instruction and mstatus.tw = 1. If supervisor mode is present: - when a wfi instruction is executed, an illegal exception should be triggered if either the current mode is user or the mode is supervisor and mstatus.tw is set. Plus, if the hypervisor extensions are enabled: - a virtual instruction exception should be raised when a wfi is executed from virtual-user or virtual-supervisor and hstatus.vtw is set. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210420213656.85148-1-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng2021-06-082-8/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the Microchip Icicle Kit machine only supports using '-bios' to load the HSS, and does not support '-kernel' for direct kernel booting just like other RISC-V machines do. One has to use U-Boot which is chain-loaded by HSS, to load a kernel for testing. This is not so convenient. Adding '-kernel' support together with the existing '-bios', we follow the following table to select which payload we execute: -bios | -kernel | payload ------+------------+-------- N | N | HSS Y | don't care | HSS N | Y | kernel This ensures backwards compatibility with how we used to expose '-bios' to users. When '-kernel' is used for direct boot, '-dtb' must be present to provide a valid device tree for the board, as we don't generate device tree. When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload like U-Boot or OS kernel directly. Documentation is updated to describe the direct kernel boot. Note as of today there is still no PolarFire SoC support in the upstream Linux kernel hence the document does not include instructions for that. It will be updated in the future. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: Use macros for BIOS image namesBin Meng2021-06-084-12/+11
| | | | | | | | | | | | | | | | | | | | The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs/system/riscv: sifive_u: Document '-dtb' usageBin Meng2021-06-081-6/+41
| | | | | | | | | | | | | | | | | | | | Update the 'sifive_u' machine documentation to mention the '-dtb' option that can be used to pass a custom DTB to QEMU. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs/system/riscv: Correct the indentation level of supported devicesBin Meng2021-06-082-25/+25
| | | | | | | | | | | | | | | | | | | | The supported device bullet list has an additional space before each entry, which makes a wrong indentation level. Correct it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-082-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the compatible string in the upstream Linux kernel. "riscv,plic0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-083-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the compatible strings for the SiFive test device node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-06-0719-28/+30
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial branch pull request 20210607 # gpg: Signature made Mon 07 Jun 2021 19:56:43 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: vhost-vdpa: Remove redundant declaration of address_space_memory scripts/oss-fuzz: Fix typo in documentation target/mips: Fix 'Uncoditional' typo target/hppa: Remove unused 'memory.h' header hw/display/macfb: Classify the "nubus-macfb" as display device target/nios2: fix page-fit instruction count docs: fix broken reference linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[] misc: Correct relative include path i386/kvm: The value passed to strerror should be positive target/riscv: Do not include 'pmp.h' in user emulation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * vhost-vdpa: Remove redundant declaration of address_space_memoryXie Yongji2021-06-052-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The symbol address_space_memory are already declared in include/exec/address-spaces.h. So let's add this header file and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h. Signed-off-by: Xie Yongji <xieyongji@bytedance.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20210517123246.999-1-xieyongji@bytedance.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * scripts/oss-fuzz: Fix typo in documentationPhilippe Mathieu-Daudé2021-06-051-1/+1
| | | | | | | | | | | | | | | | | | While we only use stdin, the chardev is named 'stdio'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20210602170759.2500248-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé2021-06-051-3/+3
| | | | | | | | | | | | | | | | | | Fix Uncoditional -> Unconditional typo. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210602170759.2500248-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * target/hppa: Remove unused 'memory.h' headerPhilippe Mathieu-Daudé2021-06-051-1/+0
| | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517101558.1040191-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * hw/display/macfb: Classify the "nubus-macfb" as display deviceThomas Huth2021-06-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The "nubus-macfb" currently shows up as uncategorized device in the output of "-device help". Put it into the display category to fix this ugliness. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210531073255.46286-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * target/nios2: fix page-fit instruction countPavel Dovgalyuk2021-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes calculation of number of the instructions that fit the current page. It prevents creation of the translation blocks that cross the page boundaries. It is required for deterministic exception generation in icount mode. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <162072241046.823357.10485774346114851009.stgit@pasha-ThinkPad-X280> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * docs: fix broken referenceJohn Snow2021-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Long story short, we need a space here for the reference to work correctly. Longer story: Without the space, kerneldoc generates a line like this: one of :c:type:`MemoryListener.region_add\(\) <MemoryListener>`,:c:type:`MemoryListener.region_del\(\) Sphinx does not process the role information correctly, so we get this (my pseudo-notation) construct: <text>,:c:type:</text> <reference target="MemoryListener">MemoryListener.region_del()</reference> which does not reference the desired entity, and leaves some extra junk in the rendered output. See https://qemu-project.gitlab.io/qemu/devel/memory.html#c.MemoryListener member log_start for an example of the broken output as it looks today. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210511192950.2061326-1-jsnow@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]Philippe Mathieu-Daudé2021-06-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | Keep bitmask_transtbl in .rodata by marking the arrays const. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210517055243.830491-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * misc: Correct relative include pathPhilippe Mathieu-Daudé2021-06-054-6/+6
| | | | | | | | | | | | | | | | | | | | Headers should be included from the 'include/' directory, not from the root directory. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210516205034.694788-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * i386/kvm: The value passed to strerror should be positiveDmitry Voronetskiy2021-06-055-12/+12
| | | | | | | | | | | | | | Signed-off-by: Dmitry Voronetskiy <vda1999@yandex.ru> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210519113528.12474-1-davoronetskiy@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Physical Memory Protection is a system feature. Avoid polluting the user-mode emulation by its definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210516205333.696094-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch ↵Peter Maydell2021-06-0711-14/+203
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging A few testing and configure updates: - add the multiarch signals stress test - fix display of multi-word compiler stanzas in meson - fix quoting of multi-word compiler stazas in configure.sh - tag some acceptance tests as TCG only - make checkpatch test work harder to find clean diffs - split gprof/gconv job to avoid timeouts - fix centos8 VM build by adding --source-path - make checkpatch aware of .h.inc and .c.inc paths # gpg: Signature made Mon 07 Jun 2021 14:51:12 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-updates-070621-2: scripts/checkpatch.pl: process .c.inc and .h.inc files as C source tests/vm: expose --source-path to scripts to find extra files gitlab-ci: Split gprof-gcov job gitlab: work harder to avoid false positives in checkpatch tests/acceptance: tag various arm tests as TCG only tests/tcg/configure.sh: tweak quoting of target_compiler meson.build: fix cosmetics of compiler display tests/tcg: add a multiarch signals test to stress test signal delivery Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * scripts/checkpatch.pl: process .c.inc and .h.inc files as C sourceMatheus Ferst2021-06-071-2/+2
| | | | | | | | | | | | | | | | | | | | Change the regex used to determine whether a file should be processed as C source to include .c.inc and .h.inc extensions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210520195142.941261-1-matheus.ferst@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
| * tests/vm: expose --source-path to scripts to find extra filesAlex Bennée2021-06-073-1/+6
| | | | | | | | | | | | | | | | Currently the centos8 image expects to run an in-src build to find the kick starter file. Fix this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210602103527.32021-1-alex.bennee@linaro.org>