summary refs log tree commit diff stats
Commit message (Collapse)AuthorAgeFilesLines
* virtio-blk: simplify virtio_blk_dma_restart_cb()Stefan Hajnoczi2023-01-233-38/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio_blk_dma_restart_cb() is tricky because the BH must deal with virtio_blk_data_plane_start()/virtio_blk_data_plane_stop() being called. There are two issues with the code: 1. virtio_blk_realize() should use qdev_add_vm_change_state_handler() instead of qemu_add_vm_change_state_handler(). This ensures the ordering with virtio_init()'s vm change state handler that calls virtio_blk_data_plane_start()/virtio_blk_data_plane_stop() is well-defined. Then blk's AioContext is guaranteed to be up-to-date in virtio_blk_dma_restart_cb() and it's no longer necessary to have a special case for virtio_blk_data_plane_start(). 2. Only blk_drain() waits for virtio_blk_dma_restart_cb()'s blk_inc_in_flight() to be decremented. The bdrv_drain() family of functions do not wait for BlockBackend's in_flight counter to reach zero. virtio_blk_data_plane_stop() relies on blk_set_aio_context()'s implicit drain, but that's a bdrv_drain() and not a blk_drain(). Note that virtio_blk_reset() already correctly relies on blk_drain(). If virtio_blk_data_plane_stop() switches to blk_drain() then we can properly wait for pending virtio_blk_dma_restart_bh() calls. Once these issues are taken care of the code becomes simpler. This change is in preparation for multiple IOThreads in virtio-blk where we need to clean up the multi-threading behavior. I ran the reproducer from commit 49b44549ace7 ("virtio-blk: On restart, process queued requests in the proper context") to check that there is no regression. Cc: Sergio Lopez <slp@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-id: 20221102182337.252202-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* util/aio: Defer disabling poll mode as long as possibleChao Gao2023-01-231-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we measure FIO read performance (cache=writethrough, bs=4k, iodepth=64) in VMs, ~80K/s notifications (e.g., EPT_MISCONFIG) are observed from guest to qemu. It turns out those frequent notificatons are caused by interference from worker threads. Worker threads queue bottom halves after completing IO requests. Pending bottom halves may lead to either aio_compute_timeout() zeros timeout and pass it to try_poll_mode() or run_poll_handlers() returns no progress after noticing pending aio_notify() events. Both cause run_poll_handlers() to call poll_set_started(false) to disable poll mode. However, for both cases, as timeout is already zeroed, the event loop (i.e., aio_poll()) just processes bottom halves and then starts the next event loop iteration. So, disabling poll mode has no value but leads to unnecessary notifications from guest. To minimize unnecessary notifications from guest, defer disabling poll mode to when the event loop is about to be blocked. With this patch applied, FIO seq-read performance (bs=4k, iodepth=64, cache=writethrough) in VMs increases from 330K/s to 413K/s IOPS. Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Chao Gao <chao.gao@intel.com> Message-id: 20220710120849.63086-1-chao.gao@intel.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* Merge tag 'pull-target-arm-20230123' of ↵Peter Maydell2023-01-2328-363/+486
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Widen cnthctl_el2 to uint64_t * Unify checking for M Main Extension in MRS/MSR * bitbang_i2c, versatile_i2c: code cleanups * SME: refactor SME SM/ZA handling * Fix physical address resolution for MTE * Fix in_debug path in S1_ptw_translate * Don't set EXC_RETURN.ES if Security Extension not present * Implement DBGCLAIM registers * Provide stubs for more external debug registers * Look up ARMCPRegInfo at runtime, not translate time # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPOjQQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vreD/sGr7outToY4FSZ4GGpC1L6 # ZwF6kjmwED/8EVaGZxWOaL2/oNoEav2YSpzUbqCa79jUx5zFBE145zYknL/bZyjS # VLX9G2vFFCtwFQ9rc2wV/3JmTmMmSCnHqOZPMSVy5vrQKH6d41WFYZEvGpJmCgh6 # YWK4gnMqkuIHmSvxw+S6q9p/3jzPk7c3vy8eRcxp+AMnfSBkYu0kFXmr7yOwscRS # adT8GFrkj0our/HtYqvzclVzrxcCVF1pWrtrHK7ZSddmElIcztel+1/yQH3T6onj # aOyRj1WC3+0t9uKwUNTFSHkRUqMqr6XYvRF+cvpe5N7lbfVn57u2TwmPgUwYbZcg # 8Mbz+LRYENzTYZa59ACxJXXcG0BivXiTwyrFR8Ck0vakcWFAjDzxHOw9CgHkDwPs # Dd93b04esehIN7MY8/5CSkbx+8ey+YK+o7sofiDCMKcYwooM1Y+Ls21ZcjA5GH+n # SsXp93SgagndCydD0ftRUlDTtGL7dhzaGpRmYArjeWzOKBbAmv/WfQeH47p3bpaP # CB2RUjHzYobMGLO0yp9droOaVKqKKLtc7wGzxgJGx6j5FrN0lnCEMRrKrZJ57Q/q # z4VoRoo0I6Q994/mVanGqXx8cSucyl0Z3HbC633WvrnZXzoM7+7HlQLhpF+yd9+s # 4lHiw0rPgqXtwEfeMaESSQ== # =ubIU # -----END PGP SIGNATURE----- # gpg: Signature made Mon 23 Jan 2023 13:35:00 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits) target/arm: Look up ARMCPRegInfo at runtime target/arm: Reorg do_coproc_insn target/arm: provide stubs for more external debug registers target/arm: implement DBGCLAIM registers target/arm: Don't set EXC_RETURN.ES if Security Extension not present target/arm: Fix in_debug path in S1_ptw_translate target/arm: Fix physical address resolution for MTE target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr() target/arm/sme: Rebuild hflags in aarch64_set_svcr() target/arm/sme: Reset ZA state in aarch64_set_svcr() target/arm/sme: Reset SVE state in aarch64_set_svcr() target/arm/sme: Introduce aarch64_set_svcr() target/arm/sme: Rebuild hflags in set_pstate() helpers target/arm/sme: Reorg SME access handling in handle_msr_i() hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState hw/i2c/versatile_i2c: Drop useless casts from void * to pointer hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Look up ARMCPRegInfo at runtimeRichard Henderson2023-01-235-49/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not encode the pointer as a constant in the opcode stream. This pointer is specific to the cpu that first generated the translation, which runs into problems with both hot-pluggable cpus and user-only threads, as cpus are removed. It's also a potential correctness issue in the theoretical case of a slightly-heterogenous system, because if CPU 0 generates a TB and then CPU 1 executes it, CPU 1 will end up using CPU 0's hash table, which might have a wrong set of registers in it. (All our current systems are either completely homogenous, M-profile, or have CPUs sufficiently different that they wouldn't be sharing TBs anyway because the differences would show up in the TB flags, so the correctness issue is only theoretical, not practical.) Perform the lookup in either helper_access_check_cp_reg, or a new helper_lookup_cp_reg. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230106194451.1213153-3-richard.henderson@linaro.org [PMM: added note in commit message about correctness issue] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Reorg do_coproc_insnRichard Henderson2023-01-231-186/+186
| | | | | | | | | | | | | | | | | | | | | | Move the ri == NULL case to the top of the function and return. This allows the else to be removed and the code unindented. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230106194451.1213153-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: provide stubs for more external debug registersEvgeny Iakovlev2023-01-231-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu doesn't implement Debug Communication Channel, as well as the rest of external debug interface. However, Microsoft Hyper-V in tries to access some of those registers during an EL2 context switch. Since there is no architectural way to not advertise support for external debug, provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1 registers in the same way the rest of DCM is currently done. Do account for access traps though with access_tda. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230120155929.32384-3-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: implement DBGCLAIM registersEvgeny Iakovlev2023-01-232-0/+34
| | | | | | | | | | | | | | | | | | | | | | The architecture does not define any functionality for the CLAIM tag bits. So we will just keep the raw bits, as per spec. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230120155929.32384-2-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Don't set EXC_RETURN.ES if Security Extension not presentPeter Maydell2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In v7m_exception_taken(), for v8M we set the EXC_RETURN.ES bit if either the exception targets Secure or if the CPU doesn't implement the Security Extension. This is incorrect: the v8M Arm ARM specifies that the ES bit should be RES0 if the Security Extension is not implemented, and the pseudocode agrees. Remove the incorrect condition, so that we leave the ES bit 0 if the Security Extension isn't implemented. This doesn't have any guest-visible effects for our current set of emulated CPUs, because all our v8M CPUs implement the Security Extension; but it's worth fixing in case we add a v8M CPU without the extension in future. Reported-by: Igor Kotrasinski <i.kotrasinsk@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Fix in_debug path in S1_ptw_translateRichard Henderson2023-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | During the conversion, the test against get_phys_addr_lpae got inverted, meaning that successful translations went to the 'failed' label. Cc: qemu-stable@nongnu.org Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table walking") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1417 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230114054605.2977022-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix physical address resolution for MTERichard Henderson2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | Conversion to probe_access_full missed applying the page offset. Fixes: b8967ddf ("target/arm: Use probe_access_full for MTE") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1416 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230114031213.2970349-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr()Richard Henderson2023-01-234-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify the two helper_set_pstate_{sm,za} in this function. Do not call helper_* functions from svcr_write. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-8-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Rebuild hflags in aarch64_set_svcr()Richard Henderson2023-01-234-19/+6
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-7-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Reset ZA state in aarch64_set_svcr()Richard Henderson2023-01-232-12/+12
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-6-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Reset SVE state in aarch64_set_svcr()Richard Henderson2023-01-235-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Move arm_reset_sve_state() calls to aarch64_set_svcr(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-5-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Introduce aarch64_set_svcr()Richard Henderson2023-01-235-4/+13
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-4-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Rebuild hflags in set_pstate() helpersRichard Henderson2023-01-232-1/+2
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-3-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/sme: Reorg SME access handling in handle_msr_i()Richard Henderson2023-01-231-11/+13
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230112102436.1913-2-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2cPhilippe Mathieu-Daudé2023-01-235-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This device model started with the Versatile board, named TYPE_VERSATILE_I2C, then ended up renamed TYPE_ARM_SBCON_I2C as per the official "ARM SBCon two-wire serial bus interface" description from: https://developer.arm.com/documentation/dui0440/b/programmer-s-reference/two-wire-serial-bus-interface--sbcon Use the latter name as a better description. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macroPhilippe Mathieu-Daudé2023-01-231-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | ARM_SBCON_I2C() macro and ArmSbconI2CState typedef are already declared via the QOM DECLARE_INSTANCE_CHECKER() macro in "hw/i2c/arm_sbcon_i2c.h". Drop the VERSATILE_I2C declarations from versatile_i2c.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2CPhilippe Mathieu-Daudé2023-01-235-7/+6
| | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CStatePhilippe Mathieu-Daudé2023-01-232-7/+6
| | | | | | | | | | | | | | | | | | | | In order to rename TYPE_VERSATILE_I2C as TYPE_ARM_SBCON_I2C (the formal ARM naming), start renaming its state. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/versatile_i2c: Drop useless casts from void * to pointerPhilippe Mathieu-Daudé2023-01-231-2/+2
| | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/bitbang_i2c: Convert DPRINTF() to trace eventsPhilippe Mathieu-Daudé2023-01-232-12/+10
| | | | | | | | | | | | | | | | | | | | Convert the remaining DPRINTF debug macro uses to tracepoints. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20230111085016.44551-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/bitbang_i2c: Trace state changesPhilippe Mathieu-Daudé2023-01-232-5/+31
| | | | | | | | | | | | | | | | | | | | Trace bitbang state machine changes with trace events. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20230111085016.44551-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/bitbang_i2c: Change state calling bitbang_i2c_set_state() helperPhilippe Mathieu-Daudé2023-01-231-8/+15
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20230111085016.44551-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/bitbang_i2c: Remove unused dummy MemoryRegionPhilippe Mathieu-Daudé2023-01-231-5/+2
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20230111085016.44551-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i2c/bitbang_i2c: Define TYPE_GPIO_I2C in public headerPhilippe Mathieu-Daudé2023-01-233-2/+4
| | | | | | | | | | | | | | | | | | | | | | Define TYPE_GPIO_I2C in the public "hw/i2c/bitbang_i2c.h" header and use it in hw/arm/musicpal.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20230111085016.44551-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Unify checking for M Main Extension in MRS/MSRDavid Reiss2023-01-231-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with the Main Extension. However, the MRS instruction did not check this, and the MSR instruction handled it inconsistently (warning BASEPRI, but silently ignoring writes to BASEPRI_NS). Unify this behavior and always warn when reading or writing any of these registers if the extension is not present. Signed-off-by: David Reiss <dreiss@meta.com> Message-id: 167330628518.10497.13100425787268927786-0@git.sr.ht Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Widen cnthctl_el2 to uint64_tRichard Henderson2023-01-231-1/+1
|/ | | | | | | | | | | | This is a 64-bit register on AArch64, even if the high 44 bits are RES0. Because this is defined as ARM_CP_STATE_BOTH, we are asserting that the cpreg field is 64-bits. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1400 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230115171633.3171890-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'pull-riscv-to-apply-20230120' of ↵Peter Maydell2023-01-2024-536/+713
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Second RISC-V PR for QEMU 8.0 * riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPKRP0ACgkQIeENKd+X # cFTHTwgAkyRDxrLepvI0KNaT0+cUBh+3QFlJ5JRtVnDW+5R+3aGT72PTS7Migqoh # H3IFCB2mcSdQvyjj2jDFlrFd0oVIaqE0+bnhouS/4nHB5S/vmapHi4Mc74Vv1CMB # rgXScL+C5gDOH1I7XjqOb1FY5Vxqyhi3IzdIoj+0ysUrGmUkqx+ij/cfQL7jkH9Q # slNAkorgwgrTgMgkJ5RKd4cjyv35O4XKLAsgixVTfJ+WcxKmc/zaJOkNM/UDnmxK # k2+2P8bshZWtWscXbm3oMC5+2ow1QtFedEkhHqb4adkQIyolKL7P1TfMlCgMSvES # BKl0DUhqQ+7F77tik3GPy9spQ6LpTQ== # =ifFF # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Jan 2023 07:38:37 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu: (37 commits) hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() target/riscv: Remove helper_set_rod_rounding_mode target/riscv: Introduce helper_set_rounding_mode_chkfrm tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 target/riscv: Fix up masking of vsip/vsie accesses hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() hw/riscv/sifive_u.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/spike.c: simplify create_fdt() target/riscv: Use TARGET_FMT_lx for env->mhartid target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu: set cpu->cfg in register_cpu_props() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv/spike.c: load initrd right after riscv_load_kernel() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()Daniel Henrique Barboza2023-01-201-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") moved the initialization of fw_cfg to the virt_machine_done() callback. Problem is that the validation of fw_cfg by devices such as ramfb is done before the machine done notifier is called. Moving create_fw_cfg() to machine_done() results in QEMU failing to boot when using a ramfb device: ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA The fix is simple: move create_fw_cfg() config back to virt_machine_init(). This happens to be the same way the ARM 'virt' machine deals with fw_cfg (see machvirt_init() and virt_machine_done() in hw/arm/virt.c), so we're keeping consistency with how other machines handle this device. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson2023-01-203-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | The only setting of RISCV_FRM_ROD is from the vector unit, and now handled by helper_set_rounding_mode_chkfrm. This helper is now unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson2023-01-204-20/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new helper always validates the contents of FRM, even if the new rounding mode is not DYN. This is required by the vector unit. Track whether we've validated FRM separately from whether we've updated fp_status with a given rounding mode, so that we can elide calls correctly. This partially reverts d6c4d3f2a69 which attempted the to do the same thing, but with two calls to gen_set_rm(), which is both inefficient and tickles an assertion in decode_save_opc. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldstRichard Henderson2023-01-201-1/+1
| | | | | | | | | | | | | | | | | | | | We failed to update this with the w^x split, so misses the fact that true pc-relative offsets are usually small. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker2023-01-201-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Per the AIA specification, writes to stimecmp from VS level should trap when hvictl.VTI is set since the write may cause vsip.STIP to become unset. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker2023-01-201-24/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current logic attempts to shift the VS-level bits into their correct position in mip while leaving the remaining bits in-tact. This is both pointless and likely incorrect since one would expect that any new, future VS-level interrupts will get their own position in mip rather than sharing with their (H)S-level equivalent. Fix this, and make the logic more readable, by just making off the VS-level bits and shifting them into position. This also fixes reads of vsip, which would only ever report vsip.VSSIP since the non-writable bits got masked off as well. Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32") Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza2023-01-204-8/+8
| | | | | | | | | | | | | | | | | | | | | | There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza2023-01-204-18/+18
| | | | | | | | | | | | | | | | | | | | | | There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()Daniel Henrique Barboza2023-01-201-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | create_fdt_socket_cpus() writes a different 'mmu-type' value if we're running in 32 or 64 bits. However, the flag is being calculated during virt_machine_init(), and is passed around in create_fdt(), then create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of the intermediate functions are using the flag, which is a bit misleading. Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it using the already available RISCVVirtState pointer. This will also change the signature of create_fdt_socket() and create_fdt(), making it clear that these functions don't do anything special when we're running in 32 bit mode. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'cmdline' isn't being used. Remove it. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). 'mem_size' is being set as machine->ram_size by the caller. Retrieve it via ms->ram_size. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/virt.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-3/+2
| | | | | | | | | | | | | | | | | | | | 'mem_size' and 'cmdline' aren't being used. Remove them. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/spike.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-3/+1
| | | | | | | | | | | | | | | | | | | | 'mem_size' and 'cmdline' are unused. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng2023-01-201-3/+3
| | | | | | | | | | | | | | | | | | | | env->mhartid is currently casted to long before printed, which drops the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230109152655.340114-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza2023-01-201-194/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> [ Changes by AF: - Rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza2023-01-202-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive boards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with what riscv_cpu_realize() expects. This will also make the cpu_init() functions even more alike, but at this moment we would need some design changes in how we're initializing extensions/attributes (e.g. some CPUs are setting cfg options after register_cpu_props(), so we can't simply add the function to a common post_init() hook) to make a common cpu_init() code across all CPUs. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-208-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-206-12/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza2023-01-203-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing riscv_load_kernel(), write 'bootargs' in the same code path as riscv_load_kernel(). Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-206-40/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the FDT inside riscv_load_initrd(), sparing callers from having to manage start/end addrs to write the FDT themselves. An 'if (fdt)' check is already inserted at the end of the function because we'll end up using it later on with other boards that doesn´t have a FDT. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv/spike.c: load initrd right after riscv_load_kernel()Daniel Henrique Barboza2023-01-201-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>