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* hw/arm/aspeed: Add GB200 BMC targetEd Tanous2025-07-033-0/+102
| | | | | | | | | | | | | | | GB200nvl72 is a system for for accelerated compute. This is a model for the BMC target within the system. This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts from: [1] https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-4-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* docs: add support for gb200-bmcEd Tanous2025-07-031-2/+2
| | | | | | | | | This patch updates the docs for support of gb200-bmc. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/arm/aspeed: Add second SPI chip to Aspeed modelEd Tanous2025-07-032-0/+4
| | | | | | | | | | Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* aspeed: Deprecate the ast2700a0-evb machineJamin Lin2025-07-031-0/+8
| | | | | | | | | | | | The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703052400.2927831-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/qtest: Add test for ASPEED SCUTan Siewert2025-07-032-0/+232
| | | | | | | | | | | | | | | | | | | | | This adds basic tests for the ASPEED System Control Unit (SCU) and its protection mechanism on the AST2500 and AST2600 platforms. The tests verify: - That SCU protection registers can be unlocked and locked again - That modifying the primary protection register on AST2600 also affects the secondary one - That writes to protected SCU registers are blocked unless protection registers are unlocked explicitly These tests ensure proper emulation of hardware locking behaviour and help catch regressions in SCU access logic. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250630112646.74944-1-tan@siewert.io [ clg: Reordered file list in meson.build ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/misc/aspeed_scu: Handle AST2600 protection key registers correctlyTan Siewert2025-07-031-2/+14
| | | | | | | | | | | | | | | The AST2600 SCU has two protection key registers (0x00 and 0x10) that both need to be unlocked. (Un-)locking 0x00 modifies both protection key registers, while modifying 0x10 only modifies itself. This commit updates the SCU write logic to reject writes unless both protection key registers are unlocked, matching the behaviour of real hardware. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250619085329.42125-1-tan@siewert.io Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/arm/aspeed: add Catalina machine typePatrick Williams2025-07-034-0/+228
| | | | | | | | | | | | | | | | | | | | | Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of 6.16-rc2. The i2c model is as complete as the current QEMU models support, but in some cases I substituted devices that are close enough for present functionality. Strap registers are were verified with hardware. This has been tested with an openbmc image built from [2]. Add a functional test in line with Bletchley, pointing at an image obtained from the OpenBMC Jenkins server. [1]: https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts [2]: https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0 Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/arm/aspeed: bletchley: update hw strap valuesPatrick Williams2025-07-031-3/+2
| | | | | | | | | | | | | | | | Update the Bletchley hardware strap register values per actual hardware: ``` root@bmc:~# devmem 0x1e6e2500 0x00002000 root@bmc:~# devmem 0x1e6e2510 0x00000801 ``` Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619035850.2682690-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700Jamin Lin2025-07-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | According to the datasheet: BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter. BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished. Firmware polls BIT[6] to determine when measurement is complete. The flag can be cleared by writing BIT[1] to 0. To simulate this hardware behavior in QEMU: If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid firmware hanging during polling. If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match hardware semantics. The initial value of this register is initialized to 0x80, reflecting the default value confirmed from an EVB register dump. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700Jamin Lin2025-07-031-0/+3
| | | | | | | | | | | | | | | | | | | | | On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate that DDR training has completed, thus skipping the dram_init(). To align with the recent U-Boot changes, where the Main Control Register's BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in the SDMC Main Control Register at reset time. This allows both the main U-Boot stage to correctly detect and bypass DRAM initialization when running under QEMU. Reference: - QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a - U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2025-07-0316-33/+33
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Fix file names of renamed files in comments and MAINTAINERS * Fix the "deprecated props" in QOM on s390x * Fix URL of the aarch64_sbsaref_freebsd functional test * Fix some trouble with trible # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmhlZckRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVIZhAAltzQ9+lZYa0A5NcgbFlVSmL/E6qDIMXG # AJcNul3dgrIVcCrxN17dBmU4ftemjQCpcw7I4fL0G0CrAMdB9Yp991tis1SwycNX # HEDY8THEE7EiOEKxBHtUFo8JbsnT+lcCwNnpvu6RXwnTN4TjT386OwBSeKv4mhHt # LFoUnX5yZqJQD1bzcrUeo+OBoXrnMkeJRuOTFXval1AGBT4q0G5mMtAcj93gONNe # hKdXhYst4XYLZIe2TJAdsbKs5Ics5UZ9rkSIC8tw1drt+iueSSSHNoPsg2AP8Ueg # iqElX3tzzb/P7QF/LWIfu55WLMbP2C2l6Pb37sdZf8Y1QpRaA/6fxQrNRoVLYfdP # 2Gqtxd8Ynn74LUxOpW+gi90mmrZpIL+M06Al0bzpI+KmWOaZxpBd0E3r5BIO1Ghb # /7XIn9svlVpBXd5V3M7Myg1BKAlJJ6GtuMMDBv8Yym6bTD+bdjGk28k/uvt6BSpq # qiMVjKrmmAO4zBkj3OZUKYoqkktf6mjso0xjXxkI2GTQ44dgvXXluwHF8F5LzBPz # y2X+KGhf/vfXqP7cAGpmFH3SjDqngdqvuBT/pDO/VWRUhyz8lM6DyPsdVhS7KrXl # QByt4FkCzYS+o9kc2Hlobj+ujjEPG+1ffSDDweioYYygsZny+8GBgD5D31e5cPsP # 9/Uc75aJD88= # =SEr8 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Jul 2025 13:00:57 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu: tests/functional/test_aarch64_sbsaref_freebsd: Fix the URL of the ISO image target/s390x: A fix for the trouble with tribles target/s390x: set has_deprecated_props flag MAINTAINERS: fix paths for relocated files treewide: fix paths for relocated files in comments treewide: update docs file extensions (.txt -> .rst) in comments MAINTAINERS: fix VMware filename typo (vwm -> vmw) MAINTAINERS: fix vendor capitalization (Vmware -> VMware) MAINTAINERS: update docs file extensions (.txt -> .rst) Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/functional/test_aarch64_sbsaref_freebsd: Fix the URL of the ISO imageThomas Huth2025-07-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The original image has been removed from the server, so the test currently fails if it has to fetch the asset, but we can still download the ISO from the archive server. While we're at it, prefer the XZ compressed image, it's much smaller and thus the download should be faster. Message-ID: <20250701105809.366180-1-thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x: A fix for the trouble with triblesThomas Huth2025-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | While Tribbles are cute, it should be "triple store" here, not "trible store". Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250701194241.434183-1-thuth@redhat.com>
| * target/s390x: set has_deprecated_props flagCollin Walling2025-07-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Now that the deprecated_props is an optional field, the expansion method must now set the "has_deprecated_props" flag in order for the data to be output from the response. Fixes: 448553bb7c (qapi: Make CpuModelExpansionInfo::deprecated-props optional and generic) Signed-off-by: Collin Walling <walling@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250630024404.940882-1-walling@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * MAINTAINERS: fix paths for relocated filesSean Wei2025-07-021-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several files were renamed in previous commits, causing their entries in MAINTAINERS to reference outdated paths. This prevents scripts/get_maintainer.pl from correctly matching these files to their maintainers. Update the filenames to reflect their current locations so that maintainer lookup works properly. Related commits --------------- c45460decbd (Oct 2023) hw/input/stellaris_input: Rename to stellaris_gamepad Rename include/hw/input/{gamepad.h => stellaris_gamepad.h} 4faf359accb (Nov 2020) docs: Move virtio-net-failover.rst into the system manual Rename docs/{ => system}/virtio-net-failover.rst 89857312f32 (Apr 2024) hw/usb: move stubs out of stubs/ Rename stubs/usb-dev-stub.c => hw/usb/bus-stub.c f2604d8508a (Apr 2024) hw/virtio: move stubs out of stubs/ Rename stubs/virtio-md-pci.c => hw/virtio/virtio-md-stubs.c 2c888febdfa (Apr 2024) memory-device: move stubs out of stubs/ Rename stubs/memory_device.c => hw/mem/memory-device-stubs.c d481cec7565 (Oct 2024) migration: Move cpu-throttle.c from system to migration Rename {system => migration}/cpu-throttle.c 864a3fa4392 (Jan 2023) monitor: Rename misc.c to hmp-target.c Rename monitor/{misc.c => hmp-target.c} Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <374597a7-94e4-45b2-9617-35183db3ea9d@sean.taipei> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * treewide: fix paths for relocated files in commentsSean Wei2025-07-024-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the docs directory restructuring, several comments refer to paths that no longer exist. Replace these references to the current file locations so readers can find the correct files. Related commits --------------- 189c099f75f (Jul 2021) docs: collect the disparate device emulation docs into one section Rename docs/system/{ => devices}/nvme.rst 5f4c96b779f (Feb 2023) docs/system/loongarch: update loongson3.rst and rename it to virt.rst Rename docs/system/loongarch/{loongson3.rst => virt.rst} fe0007f3c1d (Sep 2023) exec: Rename cpu.c -> cpu-target.c Rename cpus-common.c => cpu-common.c 42fa9665e59 (Apr 2025) exec: Restrict 'cpu_ldst.h' to accel/tcg/ Rename include/{exec/cpu_ldst.h => accel/tcg/cpu-ldst.h} Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.06@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * treewide: update docs file extensions (.txt -> .rst) in commentsSean Wei2025-07-028-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several source comments still refer to docs with the old .txt extension that were previously converted to reStructuredText. Update these references to use the correct .rst extensions to maintain accurate in-tree documentation pointers. No functional changes. Related commits: 50f8174c5c1 (Jul 2021): docs/specs/acpi_nvdimm: Convert to rST f054eb1c920 (Jul 2021): docs/specs/acpi_pci_hotplug: Convert to rST 912fb3678b8 (Sep 2023): docs/specs/vmgenid: Convert to rST bb1cff6ee04 (Sep 2023): docs/specs/ivshmem-spec: Convert to rST 55ff468f781 (Jan 2022): docs: Rename ppc-spapr-hotplug.txt to .rst Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.05@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * MAINTAINERS: fix VMware filename typo (vwm -> vmw)Sean Wei2025-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The entry for the VMware PVSCSI spec uses "vwm" instead of "vmw", which does not match any file in the tree. Correct the path so scripts/get_maintainer.pl can match the file. Signed-off-by: Sean Wei <me@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250616.qemu.relocated.04@sean.taipei> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * MAINTAINERS: fix vendor capitalization (Vmware -> VMware)Sean Wei2025-07-021-1/+1
| | | | | | | | | | | | | | | | | | "VMware" is the vendor's official spelling. Adjust the spelling in MAINTAINERS for consistency. Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.03@sean.taipei> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * MAINTAINERS: update docs file extensions (.txt -> .rst)Sean Wei2025-07-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The documentation tree has been converted to reStructuredText, but two entries in MAINTAINERS still point to the removed *.txt files. This prevents scripts/get_maintainer.pl from matching the documents. Update those entries to *.rst so the maintainer script works again. Related commits: 8472cc5dbe6 (Sep 2023): docs/specs/vmw_pvscsi-spec: Convert to rST 8e72ceee5cd (Jun 2022): Rename docs/specs/fw_cfg.txt to .rst Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.01@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-10.1-maintainer-june-2025-020725-1' of ↵Stefan Hajnoczi2025-07-0322-42/+863
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/stsquad/qemu into staging Maintainer updates for June (gitlab, semihosting, plugins, virtio-gpu) - mark s390x runner system tests as allow_fail - build semihosting once - add register write support to plugins - add virtual memory write support to plugins - add harder memory read/write support to plugins - add patcher plugin and tests - re-stock virtio-gpu MAINTAINERS - fix context init for Venus fences * tag 'pull-10.1-maintainer-june-2025-020725-1' of https://gitlab.com/stsquad/qemu: virtio-gpu: support context init multiple timeline MAINTAINERS: add Akihiko and Dmitry as reviewers MAINTAINERS: add myself to virtio-gpu for Odd Fixes plugins: Update plugin version and add notes plugins: Add patcher plugin and test tests/tcg: Remove copy-pasted notes and from i386 and add x86_64 system tests to tests plugins: Add memory hardware address read/write API plugins: Add memory virtual address write API plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacks plugins: Add register write API gdbstub: Expose gdb_write_register function to consumers of gdbstub semihosting/uaccess: Compile once semihosting/uaccess: Remove uses of target_ulong type tests/functional: Add PCI hotplug test for aarch64 gitlab: mark s390x-system to allow failures Conflicts: tests/functional/meson.build Context conflict with commit 7bc86ccbb59f ("tests/functional: test device passthrough on aarch64"), keep both changes to tests_aarch64_system_thorough[].
| * virtio-gpu: support context init multiple timelineYiwei Zhang2025-07-021-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to be handled on the specific timeline within that target context. Before this change, venus fencing is completely broken if the host driver doesn't support implicit fencing with external memory objects. Frames can go backwards along with random artifacts on screen if the host driver doesn't attach an implicit fence to the render target. The symptom could be hidden by certain guest wsi backend that waits on a venus native VkFence object for the actual payload with limited present modes or under special configs. e.g. x11 mailbox or xwayland. After this change, everything related to venus fencing starts making sense. Confirmed this via guest and host side perfetto tracing. Cc: qemu-stable@nongnu.org Fixes: 94d0ea1c1928 ("virtio-gpu: Support Venus context") Signed-off-by: Yiwei Zhang <zzyiwei@gmail.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Message-Id: <20250518152651.334115-1-zzyiwei@gmail.com> [AJB: remove version history from commit message] Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Message-ID: <20250627112512.1880708-16-alex.bennee@linaro.org>
| * MAINTAINERS: add Akihiko and Dmitry as reviewersAlex Bennée2025-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Thanks for volunteering to help. Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250603110204.838117-9-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-15-alex.bennee@linaro.org>
| * MAINTAINERS: add myself to virtio-gpu for Odd FixesAlex Bennée2025-07-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Seeing as I've taken a few patches to here now I might as well put myself forward to maintain virtio-gpu. I've marked it as Odd Fixes as it is not my core focus. If someone with more GPU experience comes forward we can always update again. Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250603110204.838117-8-alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-14-alex.bennee@linaro.org>
| * plugins: Update plugin version and add notesRowan Hart2025-07-021-1/+8
| | | | | | | | | | | | | | | | | | | | | | This patch updates the plugin version to gate new APIs and adds notes describing what has been added. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-9-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-13-alex.bennee@linaro.org>
| * plugins: Add patcher plugin and testRowan Hart2025-07-026-2/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a plugin that exercises the virtual and hardware memory read-write API functions added in a previous patch. The plugin takes a target and patch byte sequence, and will overwrite any instruction matching the target byte sequence with the patch. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-8-rowanbhart@gmail.com> [AJB: tweak Makefile, use uintptr_t for pointer stuffing] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-12-alex.bennee@linaro.org>
| * tests/tcg: Remove copy-pasted notes and from i386 and add x86_64 system ↵Rowan Hart2025-07-021-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | tests to tests The x86_64-softmmu Makefile seems to have been copy-pasted from the i386 Makefile at some point in the past. Cleaning up a vestigial unused variable and removing some outdated comments. Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-7-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-11-alex.bennee@linaro.org>
| * plugins: Add memory hardware address read/write APIRowan Hart2025-07-022-0/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functions to the plugins API to allow plugins to read and write memory via hardware addresses. The functions use the current address space of the current CPU in order to avoid exposing address space information to users. A later patch may want to add a function to permit a specified address space, for example to facilitate architecture-specific plugins that want to operate on them, for example reading ARM secure memory. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-6-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-10-alex.bennee@linaro.org>
| * plugins: Add memory virtual address write APIRowan Hart2025-07-022-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functions to the plugins API to allow reading and writing memory via virtual addresses. These functions only permit doing so on the current CPU, because there is no way to ensure consistency if plugins are allowed to read or write to other CPUs that aren't currently in the context of the plugin. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-5-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-9-alex.bennee@linaro.org>
| * plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacksRowan Hart2025-07-026-6/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functionality to enforce the requested QEMU_PLUGIN_CB_ flags level passed when registering a callback function using the plugins API. Each time a callback is about to be invoked, a thread-local variable will be updated with the level that callback requested. Then, called API functions (in particular, the register read and write API) will call qemu_plugin_get_cb_flags() to check the level is at least the level they require. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-4-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-8-alex.bennee@linaro.org>
| * plugins: Add register write APIRowan Hart2025-07-022-24/+56
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a function to the plugins API to allow plugins to write register contents. It also moves the qemu_plugin_read_register function so all the register-related functions are grouped together in the file. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-3-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-7-alex.bennee@linaro.org>
| * gdbstub: Expose gdb_write_register function to consumers of gdbstubRowan Hart2025-07-022-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exposes the gdb_write_register function from gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in plugins to write register contents. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Julian Ganz <neither@nut.email> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-2-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-6-alex.bennee@linaro.org>
| * semihosting/uaccess: Compile oncePhilippe Mathieu-Daudé2025-07-021-4/+1
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250526095213.14113-3-philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-5-alex.bennee@linaro.org>
| * semihosting/uaccess: Remove uses of target_ulong typePhilippe Mathieu-Daudé2025-07-022-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace target_ulong by vaddr or size_t types to match cpu_memory_rw_debug() prototype in "exec/cpu-common.h": > int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, > void *ptr, size_t len, > bool is_write); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250526095213.14113-2-philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-4-alex.bennee@linaro.org>
| * tests/functional: Add PCI hotplug test for aarch64Gustavo Romero2025-07-023-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and hot-unplug on arm64. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250528203137.1654964-1-gustavo.romero@linaro.org> [AJB: trimmed boilerplate for checkpatch, simplified invocations] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-3-alex.bennee@linaro.org>
| * gitlab: mark s390x-system to allow failuresAlex Bennée2025-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | The system tests (usually qos-test or migration-test) prove to be very susceptible on the s390x runners. Although we have boosted memory and virtual CPUs on the runners problems persist. For now mark test as allow_failure so the its clear on the CI UI when checking test results. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-2-alex.bennee@linaro.org>
* | Merge tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi2025-07-0242-1058/+1433
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * MAINTAINERS update for arm hvf * target/arm: Make RETA[AB] UNDEF when pauth is not implemented * target/arm: Refactoring of ID register value storage * target/arm: Various refactoring/cleanup patches * virt: Don't show an ITS in ACPI tables when no ITS is present * tests/functional: test device passthrough on aarch64 * tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhkE/IZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vNeD/9ZcHiqTxLyuurYntf63VLP # 55NRozF0By7f83dOja5r+NWeGSPqhDBO05PpBVArt+giE2dkkVCoJ5stNrls5ACl # oi5glXQL/bW+A3nN+WmcD+s2RMVHn5jZ6f5ChRsFo2bWYl0rtrR1raC/wl415ag/ # MMRjbXj6sabEITY7794KBN4M5RDVS+Zcu7dzPZecsttbxLIGLBvvJ0bFSmh91tH4 # Tyy889v2GHou1BxSWVcSWNCTQ9jLYV7a+VHHs4uTlsBc3Pw7LXS4DcPhEdfZ3+gy # RaZUu1Eq213qd3r75FqFgR4mrY/nIm/CXd+mWjC5LsLOX0BYQKlAFiDH599AeZV3 # f1Wa0+POJDSKLDux+hPu3/2eeggI4d5XKAW9dgCYKicCtfhFEKXmTtaJtZyW+vTR # Vpl8SDVoljDd3q/045CXzOdM5N+5xj2WNNNKYYW4stHJrAIxa88pBeK2bqzT372x # V8FENVzK+7owTibi63XEshgdVlBcCB9Xpp+9p4TEbMZcd8EEUVDFC5F6iF9hNUYT # s1cqphTVscWDXxkTSok6POHOIvotRdT7EcIVQ9VfJxVREGrtWkioDii1O+olMhyF # uoeoxkFE1Jih4LQz937pqCCgP0PPd9DMtXdX/WeiAcZSDEHlO8gbRiIIyf11qL2i # aiMIF0rHY9PvxIisnukkLQ== # =x5Ur # -----END PGP SIGNATURE----- # gpg: Signature made Tue 01 Jul 2025 12:59:30 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu: (43 commits) tests/functional: test device passthrough on aarch64 tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator tests/functional: Add hvf_available() helper tests/functional: Require TCG to run Aarch64 imx8mp-evk test tests/functional: Restrict nested Aarch64 Xen test to TCG tests/functional: Set sbsa-ref machine type in each test function hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() hw/arm/virt: Make EL2 accelerator check an accept-list hw/arm/virt: Make EL3-guest accel check an accept-list target/arm: Restrict system register properties to system binary target/arm/hvf: Pass @target_el argument to hvf_raise_exception() target/arm: Correct KVM & HVF dtb_compatible value target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event accel/hvf: Trace VM memory mapping target/arm/hvf: Trace hv_vcpu_run() failures target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() target/arm: Unify gen_exception_internal() target/arm: Reduce arm_cpu_post_init() declaration scope target/arm: Remove arm_handle_psci_call() stub ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | tests/functional: test device passthrough on aarch64Pierrick Bouvier2025-07-012-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test allows to document and exercise device passthrough, using a nested virtual machine setup. Two disks are generated and passed to the VM, and their content is compared to original images. Guest and nested guests commands are executed through two scripts, and init used in both system is configured to trigger a kernel panic in case any command fails. This is more reliable and readable than executing all commands through prompt injection and trying to guess what failed. Initially, this test was supposed to test smmuv3 nested emulation (combining both stages of translation), but I could not find any setup (kernel + vmm) able to do the passthrough correctly, despite several tries. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250627200222.5172-1-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/functional: Expand Aarch64 SMMU tests to run on HVF acceleratorPhilippe Mathieu-Daudé2025-07-011-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250623121845.7214-27-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/functional: Add hvf_available() helperPeter Maydell2025-07-013-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250623121845.7214-26-philmd@linaro.org [PMM: tweaks to satisfy the python linter CI job] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/functional: Require TCG to run Aarch64 imx8mp-evk testPhilippe Mathieu-Daudé2025-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx8mp-evk machine can only run with the TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250623121845.7214-25-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/functional: Restrict nested Aarch64 Xen test to TCGPhilippe Mathieu-Daudé2025-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently QEMU only support accelerating EL0 and EL1, so features requiring EL2 (like virtualization) or EL3 must be emulated with TCG. On macOS this test fails: qemu-system-aarch64: mach-virt: HVF does not support providing Virtualization extensions to the guest CPU Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-24-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/functional: Set sbsa-ref machine type in each test functionPhilippe Mathieu-Daudé2025-07-013-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fetch_firmware() is only about fetching firmware. Set the machine type and its default console in test_sbsaref_edk2_firmware(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> Message-id: 20250623121845.7214-23-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definitionPhilippe Mathieu-Daudé2025-07-011-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define RAMLIMIT_BYTES using the TiB definition and display the error parsed with size_to_str(): $ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-22-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized()Philippe Mathieu-Daudé2025-07-011-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QDev uses _post_init() during instance creation, before being realized. Since here both vCPUs and GIC are REALIZED, rename as virt_post_cpus_gic_realized() for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-21-philmd@linaro.org [PMM: also fixed up comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: Make EL2 accelerator check an accept-listPhilippe Mathieu-Daudé2025-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only the TCG and qtest accelerators can handle an EL2 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL2 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL2 guests then the implementor will see that they need to add it to the accept-list. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250623121845.7214-20-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: Make EL3-guest accel check an accept-listPhilippe Mathieu-Daudé2025-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only the TCG and qtest accelerators can handle an EL3 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL3 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL3 guests then the implementor will see that they need to add it to the accept-list. Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-19-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Restrict system register properties to system binaryPhilippe Mathieu-Daudé2025-07-011-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the following system-specific properties on user-mode binaries: - psci-conduit - cntfrq (ARM_FEATURE_GENERIC_TIMER) - rvbar (ARM_FEATURE_V8) - has-mpu (ARM_FEATURE_PMSA) - pmsav7-dregion (ARM_FEATURE_PMSA) - reset-cbar (ARM_FEATURE_CBAR) - reset-hivecs (ARM_FEATURE_M) - init-nsvtor (ARM_FEATURE_M) - init-svtor (ARM_FEATURE_M_SECURITY) - idau (ARM_FEATURE_M_SECURITY) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-13-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm/hvf: Pass @target_el argument to hvf_raise_exception()Philippe Mathieu-Daudé2025-07-011-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation of raising exceptions at EL2, add the 'target_el' argument to hvf_raise_exception(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Correct KVM & HVF dtb_compatible valuePhilippe Mathieu-Daudé2025-07-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8". See arch/arm64/boot/dts/foundation-v8.dts: https://github.com/torvalds/linux/commit/90556ca1ebdd Cc: qemu-stable@nongnu.org Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support") Fixes: 585df85efea ("hvf: arm: Implement -cpu host") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>