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| * target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()Bastian Koppelmann2023-06-211-1/+6
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-5-kbastian@mail.uni-paderborn.de>
| * target/tricore: ENABLE exit to main-loopBastian Koppelmann2023-06-211-0/+5
| | | | | | | | | | | | | | | | | | so we can recognize exceptions after re-enabling interrupts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-4-kbastian@mail.uni-paderborn.de>
| * target/tricore: Introduce DISAS_TARGET_EXITBastian Koppelmann2023-06-211-13/+12
| | | | | | | | | | | | | | | | | | this replaces all calls to tcg_gen_exit_tb() and moves them to tricore_tb_stop(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-3-kbastian@mail.uni-paderborn.de>
| * target/tricore: Fix RR_JLI clobbering reg A[11]Bastian Koppelmann2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | if A[r1] == A[11], then we would overwrite the destination address of the jump with the return address. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-2-kbastian@mail.uni-paderborn.de>
| * target/tricore: Fix helper_ret() not correctly restoring PSWBastian Koppelmann2023-06-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | We are always taking the TRICORE_FEATURE_13 branch as every CPU has TRICORE_FEATURE_13. For CPUs with ISA > 1.3 we have to take the else branch. We fix this by inverting the condition. We check for TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs have. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1700 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-5-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regsBastian Koppelmann2023-06-211-2/+9
| | | | | | | | | | | | | | | | | | | | some insns were not checking if an even index was used to access a 64 bit register. In the worst case that could lead to a buffer overflow as reported in https://gitlab.com/qemu-project/qemu/-/issues/1698. Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-4-kbastian@mail.uni-paderborn.de>
| * target/tricore: Correctly fix saving PSW.CDE to CSA on callBastian Koppelmann2023-06-211-1/+6
| | | | | | | | | | | | | | | | we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-3-kbastian@mail.uni-paderborn.de>
| * target/tricore: Fix out-of-bounds index in imask instructionSiqi Chen2023-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | When translating "imask" instruction of Tricore architecture, QEMU did not check whether the register index was out of bounds, resulting in a global-buffer-overflow. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698 Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612065633.149152-1-coc.cyqh@gmail.com> Message-Id: <20230612113245.56667-2-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add DISABLE insn variantBastian Koppelmann2023-06-212-1/+11
| | | | | | | | | | | | | | | | | | | | this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext as with the other DISABLE insn. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-9-kbastian@mail.uni-paderborn.de>
| * target/tricore: Implement SYCSCALL insnBastian Koppelmann2023-06-211-1/+1
| | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-8-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add shuffle insnBastian Koppelmann2023-06-214-0/+46
| | | | | | | | | | | | | | | | | | | | | | this is based on code by volumit (https://github.com/volumit/qemu/). Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 and https://gitlab.com/qemu-project/qemu/-/issues/1452. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-7-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add crc32.b insnBastian Koppelmann2023-06-214-0/+17
| | | | | | | | | | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-6-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add crc32l.w insnBastian Koppelmann2023-06-214-5/+23
| | | | | | | | | | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-5-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add LHA insnBastian Koppelmann2023-06-212-3/+20
| | | | | | | | | | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-4-kbastian@mail.uni-paderborn.de>
| * target/tricore: Add popcnt.w insnBastian Koppelmann2023-06-212-0/+8
| | | | | | | | | | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-3-kbastian@mail.uni-paderborn.de>
| * target/tricore: Introduce ISA 1.6.2 featureBastian Koppelmann2023-06-212-0/+14
|/ | | | | | | | we also introduce the tc37x CPU that implements that ISA version. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-2-kbastian@mail.uni-paderborn.de>
* Revert "cputlb: Restrict SavedIOTLB to system emulation"Peter Maydell2023-06-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d7ee93e24359703debf4137f4cc632563aa4e8d1. That commit tries to make a field in the CPUState struct not be present when CONFIG_USER_ONLY is set. Unfortunately, you can't conditionally omit fields in structs like this based on ifdefs that are set per-target. If you try it, then code in files compiled per-target (where CONFIG_USER_ONLY is or can be set) will disagree about the struct layout with files that are compiled once-only (where this kind of ifdef is never set). This manifests specifically in 'make check-tcg' failing, because code in cpus-common.c that sets up the CPUState::cpu_index field puts it at a different offset from the code in plugins/core.c in qemu_plugin_vcpu_init_hook() which reads the cpu_index field. The latter then hits an assert because from its point of view every thread has a 0 cpu_index. There might be other weird behaviour too. Mostly we catch this kind of bug because the CONFIG_whatever is listed in include/exec/poison.h and so the reference to it in build-once source files will then cause a compiler error. Unfortunately CONFIG_USER_ONLY is an exception to that: we have some places where we use it in "safe" ways in headers that will be seen by once-only source files (e.g. ifdeffing out function prototypes) and it would be a lot of refactoring to be able to get to a position where we could poison it. This leaves us in a "you have to be careful to walk around the bear trap" situation... Fixes: d7ee93e243597 ("cputlb: Restrict SavedIOTLB to system emulation") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230620175712.1331625-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'seabios-hppa-v7-pull-request' of ↵Richard Henderson2023-06-212-0/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/hdeller/qemu-hppa into staging hppa: New SeaBIOS-hppa version 7 ROM New SeaBIOS-hppa version 7 ROM to fix Debian-12 CD-ROM boot issues. Signed-off-by: Helge Deller <deller@gmx.de> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZJIExQAKCRD3ErUQojoP # XypaAP9j0YWdl1ovPiyw8fTdY5U6yCKGIjqtkXzk4egPbzkU1AD7BxMY+GbDSKv8 # Lt9K+R4cu0EVxfYsz17e780wSMLPcwc= # =M8NU # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Jun 2023 09:57:57 PM CEST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'seabios-hppa-v7-pull-request' of https://github.com/hdeller/qemu-hppa: target/hppa: New SeaBIOS-hppa version 7 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/hppa: New SeaBIOS-hppa version 7Helge Deller2023-06-202-0/+0
| | | | | | | | | | | | | | | | | | | | | | Update SeaBIOS-hppa to version 7 which fixes a boot problem with Debian-12 install CD images. The problem with Debian-12 is, that the ramdisc got bigger than what the firmware could load in one call to the LSI scsi driver. Signed-off-by: Helge Deller <deller@gmx.de>
* | Merge tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2023-06-20125-862/+872
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg: Define _CALL_AIX for clang on ppc64 accel/tcg: Build fix for macos catalina accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN accel/tcg: Restrict SavedIOTLB to system emulation accel/tcg: Use generic 'helper-proto-common.h' header plugins: Remove unused 'exec/helper-proto.h' header *: Check for CONFIG_USER_ONLY instead of CONFIG_SOFTMMU # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSRYmIdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8zbAgAlX4GcShS1OU1BDRe # b0HHHj1fFBB/9yk8f/5WuQb2snYS+pcZCez9XeT175ugovXSOz+shvmFrbRPvpfj # q8C88CIKCJRsXnhWqKWOKDqgTttu2WNXOvCe0eCZbUoGQ9K1seMvUBq6T50fNv2H # fXeHtLSu/+jiHIN3+woJqdgrkp0cko2rrpnwIpjuIsY1iz/J/VKEHmnv7Ah+GsRs # OTYnR7iN6uhBXVll14r3UCylbgdEz58sSSEi3dYYfaTRuijDwOzM0evhk6+5XzHP # DYwGdbtDE5HJOrCLiKegk80Gh6v1XVZQWnn9PdiN1eJcQsWNT9mYV9/4IsCVrsF4 # 8r5KUg== # =JmjK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Jun 2023 10:25:06 AM CEST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu: cputlb: Restrict SavedIOTLB to system emulation exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLY accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' header plugins: Remove unused 'exec/helper-proto.h' header meson: Replace softmmu_ss -> system_ss meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY accel/tcg: Check for USER_ONLY definition instead of SOFTMMU one hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU one target/ppc: Check for USER_ONLY definition instead of SOFTMMU one target/m68k: Check for USER_ONLY definition instead of SOFTMMU one target/tricore: Remove pointless CONFIG_SOFTMMU guard target/i386: Simplify i386_tr_init_disas_context() tcg/ppc: Define _CALL_AIX for clang on ppc64(be) accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN host/include/x86_64: Use __m128i for "x" constraints Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | cputlb: Restrict SavedIOTLB to system emulationPhilippe Mathieu-Daudé2023-06-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLYPhilippe Mathieu-Daudé2023-06-201-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to check the softmmu tlb availability, not if we are targetting system emulation. Besides, this code could be used by user emulation in the future. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230605230216.17202-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' headerPhilippe Mathieu-Daudé2023-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We only need lookup_tb_ptr() prototype. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230611085846.21415-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | plugins: Remove unused 'exec/helper-proto.h' headerPhilippe Mathieu-Daudé2023-06-201-1/+0
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230611085846.21415-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé2023-06-20101-714/+714
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé2023-06-2013-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we *might* have user emulation with softmmu, use the clearer 'CONFIG_SYSTEM_ONLY' key to check for system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé2023-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the CONFIG_USER_ONLY key to describe user emulation, and the CONFIG_SOFTMMU key to describe system emulation. Alias it as 'CONFIG_SYSTEM_ONLY' for parity with user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-8-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2023-06-202-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert some if() ladders for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2023-06-202-53/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert the #ifdef'ry in TCGCPUOps structure for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-6-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/ppc: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2023-06-202-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230613133347.82210-5-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/m68k: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2023-06-204-25/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert some if() ladders for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-4-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/tricore: Remove pointless CONFIG_SOFTMMU guardPhilippe Mathieu-Daudé2023-06-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't build any user emulation target for Tricore, only the system emulation. No need to check for it as it is always defined. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230613133347.82210-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/i386: Simplify i386_tr_init_disas_context()Philippe Mathieu-Daudé2023-06-201-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since cpu_mmu_index() is well-defined for user-only, we can remove the surrounding #ifdef'ry entirely. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Define _CALL_AIX for clang on ppc64(be)Richard Henderson2023-06-201-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Restructure the ifdef ladder, separating 64-bit from 32-bit, and ensure _CALL_AIX is set for ELF v1. Fixes the build for ppc64 big-endian host with clang. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leNRichard Henderson2023-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise we hit the default assert not reached. Handle it as MO_ATOM_NONE, because of size and misalignment. We already handle this correctly in do_ld16_beN. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | host/include/x86_64: Use __m128i for "x" constraintsRichard Henderson2023-06-202-13/+20
|/ / | | | | | | | | | | | | | | | | | | The macOS catalina compiler produces an error for __int128_t as the type for allocation with SSE inline asm constraint. Create a new X86Int128Union type and use the vector type for all SSE register inputs and outputs. Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge tag 'pull-target-arm-20230619' of ↵Richard Henderson2023-06-1912-1791/+2042
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix return value from LDSMIN/LDSMAX 8/16 bit atomics * Return correct result for LDG when ATA=0 * Conversion of system insns, loads and stores to decodetree * hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 * hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels * hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop * hw/arm/Kconfig: sbsa-ref uses Bochs display * imx_serial: set wake bit when we receive a data byte * docs: sbsa: document board to firmware interface * hw/misc/bcm2835_property: avoid hard-coded constants # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmSQZd0ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lvoEACHH2dWWb1WAMB4GSZbM0PA # kStY9PO7Ex87BRN6cX2T6qv40eWvZsLsgJn/igDmuv9kXIuejgw5Ri36I+Jce0ZN # +d2DyrsEH/GlIDcl86HnbG1WGB27uAu0imE8kiokNymsFbyvfLZrByi03rwPRxkp # fBVK2aFXTq1cZhjo3/43ySbF4/09ajci8uHPtnLla+WpZzoxP38GZ8qsY6WdxgEv # +ap1h2641DDCpkqqan+tEbFUczJ8QrSvUoofreOJhEAnAuqlRX8V4eiiK9McUX+P # LLUYUAMeTf9Ts2YRuJd9eUvTmxJo2WBiXFpxSvOfu5YOR5pBiDkDrGLkbY5bUvNu # Qte/O0gEG0GBwZptCnUWJtF1DoMDAnPjB3JjuBkAo0N5ch7G/McoGfNYEaNEbb6N # uKetTzlR4s0Zxv/SGxow+/kEkiDNCwna2mni563bz+L7+sRJWFEORErcNHCWckkk # 1W+C1S+pKv9EZvO4lcvJgZus6i5VlWjEOm0IrRcYO+dbA1F7T3j4miIu8JYYIPFu # IPyZytawpwq8irxTD0Z1hpsjrbkfOMb3hEbmtK4ruSCBRMBA3Zj2cd1ZrL9A00JE # xC7rLXWxUAOxEXlJ0mDLMU3XGcp5j6wbMtin9odYR0ccXOHaV8dplzLNgAusXtWO # GqKcq+m7oeSklKl/YIJsuQ== # =5BGp # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Jun 2023 04:27:41 PM CEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20230619' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits) hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property hw/misc/bcm2835_property: Replace magic frequency values by definitions hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h' docs: sbsa: document board to firmware interface imx_serial: set wake bit when we receive a data byte hw/arm/Kconfig: sbsa-ref uses Bochs display hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 target/arm: Convert load/store tags insns to decodetree target/arm: Convert load/store single structure to decodetree target/arm: Convert load/store (multiple structures) to decodetree target/arm: Convert LDAPR/STLR (imm) to decodetree target/arm: Convert load (pointer auth) insns to decodetree target/arm: Convert atomic memory ops to decodetree target/arm: Convert LDR/STR reg+reg to decodetree target/arm: Convert LDR/STR with 12-bit immediate to decodetree target/arm: Convert ld/st reg+imm9 insns to decodetree target/arm: Convert load/store-pair to decodetree ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware propertySergey Kambalin2023-06-192-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230612223456.33824-5-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 3/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE really being SoC-specific] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/misc/bcm2835_property: Replace magic frequency values by definitionsSergey Kambalin2023-06-192-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230612223456.33824-4-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 4/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitionsSergey Kambalin2023-06-191-50/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace magic property values by a proper definition, removing redundant comments. Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230612223456.33824-3-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 2/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'Sergey Kambalin2023-06-191-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230612223456.33824-2-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 1/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | docs: sbsa: document board to firmware interfaceMarcin Juszkiewicz2023-06-191-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to add more hardware information into DeviceTree to limit amount of hardcoded values in firmware. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230531171834.236569-1-marcin.juszkiewicz@linaro.org [PMM: fix format nits, add text about platform version fields from a comment in the C source file] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | imx_serial: set wake bit when we receive a data byteMartin Kaiser2023-06-192-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel added a flood check for RX data recently in commit 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This check uses the wake bit in the UART status register 2. The wake bit indicates that the receiver detected a start bit on the RX line. If the kernel sees a number of RX interrupts without the wake bit being set, it treats this as spurious data and resets the UART port. imx_serial does never set the wake bit and triggers the kernel's flood check. This patch adds support for the wake bit. wake is set when we receive a new character (it's not set for break events). It seems that wake is cleared by the kernel driver, the hardware does not have to clear it automatically after data was read. The wake bit can be configured as an interrupt source. Support this mechanism as well. Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/Kconfig: sbsa-ref uses Bochs displayMarcin Juszkiewicz2023-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20230607092112.655098-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loopPeter Maydell2023-06-191-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nrf51_timer has a free-running counter which we implement using the pattern of using two fields (update_counter_ns, counter) to track the last point at which we calculated the counter value, and the counter value at that time. Then we can find the current counter value by converting the difference in wall-clock time between then and now to a tick count that we need to add to the counter value. Unfortunately the nrf51_timer's implementation of this has a bug which means it loses time every time update_counter() is called. After updating s->counter it always sets s->update_counter_ns to 'now', even though the actual point when s->counter hit the new value will be some point in the past (half a tick, say). In the worst case (guest code in a tight loop reading the counter, icount mode) the counter is continually queried less than a tick after it was last read, so s->counter never advances but s->update_counter_ns does, and the guest never makes forward progress. The fix for this is to only advance update_counter_ns to the timestamp of the last tick, not all the way to 'now'. (This is the pattern used in hw/misc/mps2-fpgaio.c's counter.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org
| * | hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levelsPeter Maydell2023-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU allows qemu_irq lines to transfer arbitrary integers. However the convention is that for a simple IRQ line the values transferred are always 0 and 1. The A10 SD controller device instead assumes a 0-vs-non-0 convention, which happens to work with the interrupt controller it is wired up to. Coerce the value to boolean to follow our usual convention. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20230606104609.3692557-3-peter.maydell@linaro.org
| * | hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1Peter Maydell2023-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner A10 PIC model; however in the process we introduced a regression. This is because the old code was robust against the incoming 'level' argument being something other than 0 or 1, whereas the new code was not. In particular, the allwinner-sdhost code treats its IRQ line as 0-vs-non-0 rather than 0-vs-1, so when the SD controller set its IRQ line for any reason other than transmit the interrupt controller would ignore it. The observed effect was a guest timeout when rebooting the guest kernel. Handle level values other than 0 or 1, to restore the old behaviour. Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org
| * | target/arm: Convert load/store tags insns to decodetreePeter Maydell2023-06-192-177/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the instructions in the load/store memory tags instruction group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org
| * | target/arm: Convert load/store single structure to decodetreePeter Maydell2023-06-192-108/+127
| | | | | | | | | | | | | | | | | | | | | | | | Convert the ASIMD load/store single structure insns to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/arm: Convert load/store (multiple structures) to decodetreePeter Maydell2023-06-192-108/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the instructions in the ASIMD load/store multiple structures instruction classes to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org