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* s390x/pci: enable for load/store interpretationMatthew Rosato2022-09-268-1/+137
| | | | | | | | | | | | | | | | | | | | | | If the ZPCI_OP ioctl reports that is is available and usable, then the underlying KVM host will enable load/store intepretation for any guest device without a SHM bit in the guest function handle. For a device that will be using interpretation support, ensure the guest function handle matches the host function handle; this value is re-checked every time the guest issues a SET PCI FN to enable the guest device as it is the only opportunity to reflect function handle changes. By default, unless interpret=off is specified, interpretation support will always be assumed and exploited if the necessary ioctl and features are available on the host kernel. When these are unavailable, we will silently revert to the interception model; this allows existing guest configurations to work unmodified on hosts with and without zPCI interpretation support, allowing QEMU to choose the best support model available. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220902172737.170349-4-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* s390x/pci: add routine to get host function handle from CLP infoMatthew Rosato2022-09-262-16/+72
| | | | | | | | | | | | In order to interface with the underlying host zPCI device, we need to know its function handle. Add a routine to grab this from the vfio CLP capabilities chain. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Message-Id: <20220902172737.170349-3-mjrosato@linux.ibm.com> [thuth: Replace free(info) with g_free(info)] Signed-off-by: Thomas Huth <thuth@redhat.com>
* Update linux headers to v6.0-rc4Chenyi Qiang2022-09-2625-90/+538
| | | | | | | | | commit 7e18e42e4b280c85b76967a9106a13ca61c16179 Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20220915091035.3897-3-chenyi.qiang@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* configure: Add -Wno-gnu-variable-sized-type-not-at-endChenyi Qiang2022-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A Linux headers update to v6.0-rc switches some definitions from GNU 'zero-length-array' extension to the C-standard-defined flexible array member. e.g. struct kvm_msrs { __u32 nmsrs; /* number of msrs in entries */ __u32 pad; - struct kvm_msr_entry entries[0]; + struct kvm_msr_entry entries[]; }; Those (unlike the GNU zero-length-array) have some extra restrictions like 'this must be put at the end of a struct', which clang build would complain about. e.g. the current code struct { struct kvm_msrs info; struct kvm_msr_entry entries[1]; } msr_data = { } generates the warning like: target/i386/kvm/kvm.c:2868:25: error: field 'info' with variable sized type 'struct kvm_msrs' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu-variable-sized-type-not-at-end] struct kvm_msrs info; ^ In fact, the variable length 'entries[]' field in 'info' is zero-sized in GNU defined semantics, which can give predictable offset for 'entries[1]' in local msr_data. The local defined struct is just there to force a stack allocation large enough for 1 kvm_msr_entry, a clever trick but requires to turn off this clang warning. Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20220915091035.3897-2-chenyi.qiang@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x: support PRNO_TRNG instructionJason A. Donenfeld2022-09-263-0/+32
| | | | | | | | | | | | | In order for hosts running inside of TCG to initialize the kernel's random number generator, we should support the PRNO_TRNG instruction, backed in the usual way with the qemu_guest_getrandom helper. This is confirmed working on Linux 5.19. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-Id: <20220921100729.2942008-2-Jason@zx2c4.com> Reviewed-by: David Hildenbrand <david@redhat.com> [thuth: turn prno-trng off in avocado test to avoid breaking it] Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x: support SHA-512 extensionsJason A. Donenfeld2022-09-233-1/+240
| | | | | | | | | | | | | | | In order to fully support MSA_EXT_5, we have to support the SHA-512 special instructions. So implement those. The implementation began as something TweetNacl-like, and then was adjusted to be useful here. It's not very beautiful, but it is quite short and compact, which is what we're going for. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [ restructure, add missing exception, add comments, fixup CPU model ] Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20220922153820.221811-1-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* linux-user/host/s390: Add vector instructions to host_signal_write()Ilya Leoshkevich2022-09-231-0/+25
| | | | | | | | | | | | | | | | | The new noexec test fails on s390x with "unexpected SEGV". This test overwrites code using libc's memcpy(), which uses VSTL instruction. host_signal_write() does not recognize it, which causes SEGV to be incorrectly forwarded to the test. Add all vector instructions that write to memory to host_signal_write(). Fixes: ab12c95d3f19 ("target/s390x: Make translator stop before the end of a page") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20220920113907.334144-1-iii@linux.ibm.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* s390x/tcg: Fix opcode for lzrfChristian Borntraeger2022-09-231-1/+1
| | | | | | | | | | | | | | Fix the opcode for Load and Zero Rightmost Byte (32). Fixes: c2a5c1d718ea ("target/s390x: Implement load-and-zero-rightmost-byte insns") Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Cc: qemu-stable@nongnu.org Message-Id: <20220914105750.767697-1-borntraeger@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of ↵Stefan Hajnoczi2022-09-221-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/edgarigl/qemu into staging Xilinx queue # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEErET+3BT38evtv0FRKcWWeA9ryoMFAmMraeQACgkQKcWWeA9r # yoOUUwgAz/GPBURkdzYcFbOa4VEBrCaJxCu2WvyBdj6kjEgw/ZmdXbDHfeKTr2Rl # 8mo7UWugfj1KTMqo5Tmte6+3EeNcuB9qA/flKj7wfKwLX1S0V6EFNGJn8sdNe+1r # c6fYm0bUBk9FKauUT4t3U1Zl9SGJ2Pwa8JvztVgBvvZG6G+J0bkVmw2mMXb3jaaV # skzmBuvDT0G8JkxWnpEXwznrPSHSjivqawVlBfjC5JmCjZ16bz05okju+cckfzTJ # 0VF7/27MWfVCpMtWjRSA6p+3gwLziz7xOhPe9excSVsDyAs4WdcuI+/42/MBBUIn # rlg7pNIslI9r8eP5Jyk6LcSmBsPDMA== # =GZsl # -----END PGP SIGNATURE----- # gpg: Signature made Wed 21 Sep 2022 15:45:40 EDT # gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown] # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl/qemu: hw/microblaze: pass random seed to fdt Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * hw/microblaze: pass random seed to fdtJason A. Donenfeld2022-09-211-0/+5
| | | | | | | | | | | | | | | | | | | | If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This FDT node is part of the DT specification. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
* | Merge tag 'pull-hex-20220919' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-09-222-23/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hexagon update remove unused encodings add fmin/fmax tests for signed zero # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmMou7IACgkQewJE+xLe # RCIYbQgAgjFujecgbbCJfBPVMmpTXNOgk+Jt3w+jfg7/WJRZuhxAU3xB2qpismUH # 5MntMlFHAGOjlPXfg6U5AZFSw3RhlanH/RChHpVKuL6peOXFImIfEqdyVXHXfCuu # FlpQFGwJ3Rs50UJhd7lVdlx0I7lup4E4X77hFvFcZQP6aNrt6Ic1Zq5eXhEq9k2A # NnXol1R416JRT/senujYVvcTpgYVHlQCS+4dJEzKUqvFlTdo7lnAbPdjO8MPrz7B # 0NgPUGjGZJ70Dcqvd1n8HePIU1YyKTlHJNaWyTlAmw4MECyHyAJnd64jEMNECDb5 # 0BrpHcY1HCt1Rh4QratemTfJglAJlA== # =UUyr # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Sep 2022 14:57:54 EDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20220919' of https://github.com/quic/qemu: Hexagon (tests/tcg/hexagon): add fmin/fmax tests for signed zero Hexagon (target/hexagon) remove unused encodings Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | Hexagon (tests/tcg/hexagon): add fmin/fmax tests for signed zeroMatheus Tavares Bernardino2022-09-191-0/+10
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com>
| * | Hexagon (target/hexagon) remove unused encodingsTaylor Simpson2022-09-191-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove encodings guarded by ifdef that is not defined Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220606222327.7682-4-tsimpson@quicinc.com>
* | | Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ↵Stefan Hajnoczi2022-09-215-89/+118
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging m68k pull request 20220921 - several fixes for SR - implement TAS - feature cleanup # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmMrMx0SHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748UB0P/1w5w+ogpcWVp9uBPE9m6lTT8sTricWD # oGMIEG0kgpS3xTp7pZ/WeCp38IShFBfBcz5aypvR5nS/1aclyJnzGsCqyWdBe9c4 # jJJY5r7JKP2aKcolGNilNyd20ldOiaxZGe6yFLJDWi2spFbRx3iiRJ4/2NXF5Xi8 # TlHKdlDGlNLFiFNtBXMMwqvL77qJ8LH/aE4cAr8JTOb1VszKXrFxqEqxoUucRirB # u0LbM+DP3u2xXjTGLMLlMcKf9X2BXwuWBSAXslB8xWmRlX+B6fMudBFglTgbu0Cc # bpoBBqY4s3QYPb21i89osYevJAJSdrtEzkKus3xAI08ACSffb9k9m/naVJJDSSNC # HZeKVbAd7I0Xw2xzzO5yQB+7rdfgoL1miE1rs936WKHi0WWHZpdJqzl/3G3ZPhRz # NmqczF9rRR9B9SabXx5lWlhK+Ys/W7PzY+R4gc6ose0wF4T70qmVF3EoioP1c5Y8 # 6OonMpRu6L5sW5KM3IUmkBo3KcnLezlxtebfaDyaKC9tB0qg4aM14ikL36nsLFbh # 2nGExYSyMJ6U4tqpxyQxijMMSQG20vyVIup6cUsrSD+rGmbSuWZWJwsTmaAw2W6k # 6HtDgtFk40ZB1WttYupQBa/LgjshGLl28jyLI9nNEdFYb4H1JAallEERF/tb6AUD # WEiu8vcUMYEp # =IAMt # -----END PGP SIGNATURE----- # gpg: Signature made Wed 21 Sep 2022 11:51:57 EDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k: target/m68k: always call gen_exit_tb() after writes to SR target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K target/m68k: Perform writback before modifying SR target/m68k: Fix MACSR to CCR target/m68k: Implement atomic test-and-set Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | target/m68k: always call gen_exit_tb() after writes to SRMark Cave-Ayland2022-09-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any write to SR can change the security state so always call gen_exit_tb() when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | | target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68KMark Cave-Ayland2022-09-215-74/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants which define the features available for specific Motorola CPU models, rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K and add comments to clarify its usage. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | | target/m68k: Perform writback before modifying SRRichard Henderson2022-09-211-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writes to SR may change security state, which may involve a swap of %ssp with %usp as reflected in %a7. Finish the writeback of %sp@+ before swapping stack pointers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1206 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220913142818.7802-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | | target/m68k: Fix MACSR to CCRRichard Henderson2022-09-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | | target/m68k: Implement atomic test-and-setRichard Henderson2022-09-211-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is slightly more complicated than cas, because tas is allowed on data registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220829051746.227094-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | | | Merge tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi2022-09-2116-84/+278
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc patch queue for 2022-09-20: This queue contains a implementation of PowerISA 3.1B hash insns, ppc TCG insns cleanups and fixes, and miscellaneus fixes in the spapr and pnv_phb models. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYyoWlAAKCRA82cqW3gMx # ZDYhAP0eQMeA4NS3hiw7WMcAVg0pei3ZJL9oEh1UE3+MfK7MhQEA0q8qExWnQJAA # a0hfnFH9pLjI+v0f/FbFK6QJBpu/bg8= # =qT+H # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Sep 2022 15:37:56 EDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu: hw/ppc/spapr: Fix code style problems reported by checkpatch hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failure hw/ppc: spapr: Use qemu_vfree() to free spapr->htab target/ppc: Clear fpstatus flags on helpers missing it target/ppc: Zero second doubleword of VSR registers for FPR insns target/ppc: Set OV32 when OV is set target/ppc: Zero second doubleword for VSX madd instructions target/ppc: Set result to QNaN for DENBCD when VXCVI occurs target/ppc: Zero second doubleword in DFP instructions target/ppc: Remove unused xer_* macros target/ppc: Remove extra space from s128 field in ppc_vsr_t target/ppc: Merge fsqrt and fsqrts helpers target/ppc: Move fsqrts to decodetree target/ppc: Move fsqrt to decodetree target/ppc: Implement hashstp and hashchkp target/ppc: Implement hashst and hashchk target/ppc: Add HASHKEYR and HASHPKEYR SPRs Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | | hw/ppc/spapr: Fix code style problems reported by checkpatchBernhard Beschow2022-09-201-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20220919231720.163121-5-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failureXuzhou Cheng2022-09-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pnv_phb3_root_bus_info and pnv_phb4_root_bus_info are missing the instance_size initialization. This results in accessing out-of-bound memory when setting 'chip-id' and 'phb-id', and eventually crashes glib's malloc functionality with the following message: "qemu-system-ppc64: GLib: ../glib-2.72.3/glib/gmem.c:131: failed to allocate 3232 bytes" This issue was noticed only when running qtests with QEMU Windows 32-bit executable. Windows 64-bit, Linux 32/64-bit do not expose this bug though. Fixes: 9ae1329ee2fe ("ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge") Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20220920103159.1865256-29-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | hw/ppc: spapr: Use qemu_vfree() to free spapr->htabXuzhou Cheng2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spapr->htab is allocated by qemu_memalign(), hence we should use qemu_vfree() to free it. Fixes: c5f54f3e31bf ("pseries: Move hash page table allocation to reset time") Fixes: b4db54132ffe ("target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL"") Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220920103159.1865256-28-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Clear fpstatus flags on helpers missing itVíctor Colombo2022-09-201-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ppc emulation, exception flags are not cleared at the end of an instruction. Instead, the next instruction is responsible to clear it before its emulation. However, some helpers are not doing it, causing an issue where the previously set exception flags are being used and leading to incorrect values being set in FPSCR. Fix this by clearing fp_status before doing the instruction 'real' work for the following helpers that were missing this behavior: - VSX_CVT_INT_TO_FP_VECTOR - VSX_CVT_FP_TO_FP - VSX_CVT_FP_TO_INT_VECTOR - VSX_CVT_FP_TO_INT2 - VSX_CVT_FP_TO_INT - VSX_CVT_FP_TO_FP_HP - VSX_CVT_FP_TO_FP_VECTOR - VSX_CMP - VSX_ROUND - xscvqpdp - xscvdpsp[n] Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Zero second doubleword of VSR registers for FPR insnsVíctor Colombo2022-09-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FPR register are mapped to the first doubleword of the VSR registers. Since PowerISA v3.1, the second doubleword of the target register must be zeroed for FP instructions. This patch does it by writting 0 to the second dw everytime the first dw is being written using set_fpr. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Set OV32 when OV is setVíctor Colombo2022-09-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-7-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Zero second doubleword for VSX madd instructionsVíctor Colombo2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 205eb5a89e we updated most VSX instructions to zero the second doubleword, as is requested by PowerISA since v3.1. However, VSX_MADD helper was left behind unchanged, while it is also affected and should be fixed as well. This patch applies the fix for MADD instructions. Fixes: 205eb5a89e ("target/ppc: Change VSX instructions behavior to fill with zeros") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-6-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Set result to QNaN for DENBCD when VXCVI occursVíctor Colombo2022-09-201-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the ISA, for instruction DENBCD: "If an invalid BCD digit or sign code is detected in the source operand, an invalid-operation exception (VXCVI) occurs." In the Invalid Operation Exception section, there is the situation: "When Invalid Operation Exception is disabled (VE=0) and Invalid Operation occurs (...) If the operation is an (...) or format the target FPR is set to a Quiet NaN". This was not being done in QEMU. This patch sets the result to QNaN when the instruction DENBCD causes an Invalid Operation Exception. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-5-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Zero second doubleword in DFP instructionsVíctor Colombo2022-09-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting at PowerISA v3.1, the second doubleword of the registers used to store results in DFP instructions are supposed to be zeroed. From the ISA, chapter 7.2.1.1 Floating-Point Registers: """ Chapter 4. Floating-Point Facility provides 32 64-bit FPRs. Chapter 5. Decimal Floating-Point also employs FPRs in decimal floating-point (DFP) operations. When VSX is implemented, the 32 FPRs are mapped to doubleword 0 of VSRs 0-31. (...) All instructions that operate on an FPR are redefined to operate on doubleword element 0 of the corresponding VSR. (...) and the contents of doubleword element 1 of the VSR corresponding to the target FPR or FPR pair for these instructions are set to 0. """ Before, the result stored at doubleword 1 was said to be undefined. With that, this patch changes the DFP facility to zero doubleword 1 when using set_dfp64 and set_dfp128. This fixes the behavior for ISA 3.1 while keeping the behavior correct for previous ones. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Remove unused xer_* macrosVíctor Colombo2022-09-201-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Remove extra space from s128 field in ppc_vsr_tVíctor Colombo2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Merge fsqrt and fsqrts helpersVíctor Colombo2022-09-203-26/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two helpers are almost identical, differing only by the softfloat operation it calls. Merge them into one using a macro. Also, take this opportunity to capitalize the helper name as we moved the instruction to decodetree in a previous patch. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Move fsqrts to decodetreeVíctor Colombo2022-09-203-23/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Move fsqrt to decodetreeVíctor Colombo2022-09-203-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Implement hashstp and hashchkpVíctor Colombo2022-09-204-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation for instructions hashstp and hashchkp, the privileged versions of hashst and hashchk, which were added in Power ISA 3.1B. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Implement hashst and hashchkVíctor Colombo2022-09-205-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-3-victor.colombo@eldorado.org.br> [danielhb: fix block comment in excp_helper.c] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | | | target/ppc: Add HASHKEYR and HASHPKEYR SPRsVíctor Colombo2022-09-202-0/+30
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were introduced by the Power ISA 3.1B. They are used by the new instructions hashchk(p) and hashst(p). The ISA states that the Operating System should generate the value for these registers when creating a process, so it's its responsability to do so. We initialize it with 0 for qemu-softmmu, and set a random 64 bits value for linux-user. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | | | Merge tag 'pull-testing-next-200922-2' of https://github.com/stsquad/qemu ↵Stefan Hajnoczi2022-09-2143-475/+361
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Testing and CI changes: - reduce number of targets for cross_user_build - update avocado xlnx_versal test with new binaries - add explicit timeouts to a number of avocado TCG tests - reduce default timeout to 120s - update lcitool to support cross-amd64 - flatten a number of docker cross containers - clean up stale qemu/debian10 dependencies - remove obsolete Fedora VM test - add configure workaround for meson --disable-pie bug - disable --static-pie for aarch64 gitlab runner - update aarch32/aarch64 jobs to 22.04 - deprecate 32 bit big-endian MIPS as a host - remove FROM qemu/ support from docker.py - remove Debian base images now everything is flat # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmMp8Q8ACgkQ+9DbCVqe # KkQmlwf/awT+jOmAW7TjlQnUTgHJ2hyOo7EViY/nmRkPOCT3ZG32pWFHBorHPX7s # BeqZzpzCvhzaIfObnjIssx13C5QId5XjJGuTgMAnSsGhzTrp7VUJc1/bBfHcD9L2 # dJJduG+bfAkh95heBkry5EhFt2ZMui5yv9DjEH44hUUc9nwKtIQGts3H3fnVqzvv # rzLZ7c2lhdLpAxHjmjSiiD8H59lJ+DpoziaobW4D7teGgecnyGVvJ9m1YH4Rc+kM # gpLTOGMhADkQlysf5e5cvxXSJbP7YpXYrsr9X+DfEy5PMt2L3y4Yv0wiAz9ClYvm # obD4wMQS5echYvb77qS1G8A0VMEPqA== # =3oYu # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Sep 2022 12:57:51 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-next-200922-2' of https://github.com/stsquad/qemu: (30 commits) tests/docker: remove the Debian base images tests/docker: remove FROM qemu/ support from docker.py tests/docker: update and flatten debian-toolchain tests/docker: update and flatten debian-hexagon-cross tests/docker: update and flatten debian-loongarch-cross tests/docker: update and flatten debian-amd64-cross tests/lcitool: bump to latest version tests/docker: update and flatten debian-all-test-cross tests/docker: flatten debian-riscv64-test-cross Deprecate 32 bit big-endian MIPS gitlab-ci: update aarch32/aarch64 custom runner jobs gitlab-ci/custom-runners: Disable -static-pie for ubuntu-20.04-aarch64 configure: explicitly set cflags for --disable-pie tests/vm: Remove obsolete Fedora VM test tests/docker: remove amd64 qemu/debian10 dependency tests/docker: remove tricore qemu/debian10 dependency tests/docker: flatten debian-powerpc-test-cross tests/docker: update and flatten debian-sparc64-cross tests/docker: update and flatten debian-sh4-cross tests/docker: update and flatten debian-mips64-cross ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | tests/docker: remove the Debian base imagesAlex Bennée2022-09-206-74/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We no longer use these in any of our images. Clean-up the remaining comments and documentation that reference them and remove from the build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-31-alex.bennee@linaro.org>
| * | | tests/docker: remove FROM qemu/ support from docker.pyAlex Bennée2022-09-201-28/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to migrate from docker.py to building our images directly with docker/podman. Before we get there we need to make sure we don't re-introduce our layered builds so bug out if we see FROM qemu/ in a Dockerfile. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-30-alex.bennee@linaro.org>
| * | | tests/docker: update and flatten debian-toolchainAlex Bennée2022-09-202-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to the latest stable Debian. While we are at it flatten into a single dockerfile as we do not need anything from the base image to build the toolchain. This is used to build both the nios and microblaze toolchains. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-29-alex.bennee@linaro.org>
| * | | tests/docker: update and flatten debian-hexagon-crossAlex Bennée2022-09-201-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to the latest stable Debian. While we are at it flatten into a single dockerfile as we do not some of the extraneous packages from the base image to build the toolchain. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-28-alex.bennee@linaro.org>
| * | | tests/docker: update and flatten debian-loongarch-crossAlex Bennée2022-09-202-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. In this case it is a binary distribution of the toolchain anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-27-alex.bennee@linaro.org>
| * | | tests/docker: update and flatten debian-amd64-crossAlex Bennée2022-09-204-18/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now lcitool has support for building a x86_64 cross image we can use it for this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-26-alex.bennee@linaro.org>
| * | | tests/lcitool: bump to latest versionAlex Bennée2022-09-205-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need this to be able to cleanly build the x86 cross images. There are a few minor updates triggered by lcitool-refresh including adding "libslirp" to the freebsd vars and opensuse-leap which will help when we finally drop the slirp submodule from QEMU. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-25-alex.bennee@linaro.org>
| * | | tests/docker: update and flatten debian-all-test-crossAlex Bennée2022-09-203-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We also need to ensure we install clang as it is used for those builds as well. It would be nice to port this to lcitool but for now this will do. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-24-alex.bennee@linaro.org>
| * | | tests/docker: flatten debian-riscv64-test-crossAlex Bennée2022-09-203-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flatten into a single dockerfile and update to match the rest of the test cross compile dockerfiles. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-23-alex.bennee@linaro.org>
| * | | Deprecate 32 bit big-endian MIPSAlex Bennée2022-09-206-47/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's becoming harder to maintain a cross-compiler to test this host architecture as the old stable Debian 10 ("Buster") moved into LTS which supports fewer architectures. For now: - mark it's deprecation in the docs - downgrade the containers to build TCG tests only - drop the cross builds from our CI Users with an appropriate toolchain and user-space can still take their chances building it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-22-alex.bennee@linaro.org>
| * | | gitlab-ci: update aarch32/aarch64 custom runner jobsAlex Bennée2022-09-204-25/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The custom runner is now using 22.04 so we can drop our hacks to deal with broken libssh and glusterfs. The provisioning scripts will be updated in a separate commit. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-21-alex.bennee@linaro.org>
| * | | gitlab-ci/custom-runners: Disable -static-pie for ubuntu-20.04-aarch64Richard Henderson2022-09-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The project has reached the magic size at which we see /usr/aarch64-linux-gnu/lib/libc.a(init-first.o): in function `__libc_init_first': (.text+0x10): relocation truncated to fit: R_AARCH64_LD64_GOTPAGE_LO15 against \ symbol `__environ' defined in .bss section in /usr/aarch64-linux-gnu/lib/libc.a(environ.o) /usr/bin/ld: (.text+0x10): warning: too many GOT entries for -fpic, please recompile with -fPIC The bug has been reported upstream, but in the meantime there is nothing we can do except build a non-pie executable. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220823210329.1969895-1-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-20-alex.bennee@linaro.org>