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* target/ppc: Delay initialization of LPCR_UPRT for secondary cpusDavid Gibson2018-05-042-16/+12
| | | | | | | | | | | | | | | | | | | | | | In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are initialized based on on ppc64_radix_guest(). Which seems reasonable, except that ppc64_radix_guest() is based on spapr->patb_entry which is only set up in spapr_machine_reset, called _after_ cpu_ppc_set_papr() for boot cpus. Well, and the fact that modifying the SPR default value for an instance rather than a class is kind of yucky. The initialization here is really only necessary or valid for hotplugged cpus; the base cpu initialization already sets a value that's good enough for the boot cpus until the guest uses an hcall to configure it's preferred MMU mode. So, move this initialization to the rtas_start_cpu() path, at which point ppc64_radix_guest() will have a sensible value, to make sure secondary cpus come up in an MMU mode matching the existing cpus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org>
* spapr: Clean up LPCR updates from hypercallsDavid Gibson2018-05-041-30/+20
| | | | | | | | | | | | | | | | | There are several places in spapr_hcall.c where we need to update the LPCR value on all CPUs. We do this with the set_spr() helper. That's not really correct because this directly sets the SPR value, without going through the ppc_store_lpcr() helper which may need to update state based on the LPCR change. In fact, set_spr() is only ever used for the LPCR, so replace it with an explicit LPCR updated which uses the right low-level helper. While we're there, move the CPU_FOREACH() which was in every one of the callers into the new helper: set_all_lpcrs(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org>
* spapr: Make a helper to set up cpu entry point stateDavid Gibson2018-05-044-7/+15
| | | | | | | | | | | | | | Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
* spapr: Remove unhelpful helpers from rtas_start_cpu()David Gibson2018-05-041-24/+14
| | | | | | | | | | | | | | | | | | rtas_start_cpu() calls spapr_cpu_update_tb_offset() and spapr_cpu_set_endianness() to initialize certain things in the new cpu's state. This is the only caller of those helpers, and they're each only a few lines long, so we might as well just fold them into the caller. In addition, those helpers initialize state on the new cpu to match that of the first cpu. That will generally work, but might be at least logically incorrect if the first cpu has been set offline by the guest. So, instead base the state on that of the cpu invoking the RTAS call, which is obviously active already. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
* spapr: Clean up rtas_start_cpu() & rtas_stop_self()David Gibson2018-05-041-34/+32
| | | | | | | | | | | | | | | | | This makes several minor cleanups to these functions: * Follow usual convention of an early exit on error, rather than having most of the body in an if * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the RTAS call is invoked, newcpu is the cpu which we're starting * Use cpu_synchronize_state() instead of kvm_cpu_synchronize_state() directly * Remove pointless comment describing what cpu_synchronize_state() does * Use ppc_store_lpcr() instead of directly writing the register field Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
* target/ppc: Add ppc_store_lpcr() helperDavid Gibson2018-05-043-11/+13
| | | | | | | | | | | | | | | | | | There are some fields in the cpu state which need to be updated when the LPCR register is changed, which is done by ppc_hash64_update_rmls() and ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to call them afterwards to make sure the state is up to date. That's easy to get wrong. The normal way of dealing with sitautions like that is to use a helper which both updates the basic register value and the derived state. So, do that. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
* spapr: Remove support for explicitly allocated RMAsDavid Gibson2018-05-043-90/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Current POWER cpus allow for a VRMA, a special mapping which describes a guest's view of memory when in real mode (MMU off, from the guest's point of view). Older cpus didn't have that which meant that to support a guest a special host-contiguous region of memory was needed to give the guest its Real Mode Area (RMA). KVM used to provide special calls to allocate a contiguous RMA for those cases. This was useful in the early days of KVM on Power to allow it to be tested on PowerPC 970 chips as used in Macintosh G5 machines. Now, those machines are so old as to be almost irrelevant. The normal qemu deprecation process would require this to be marked deprecated then removed in 2 releases. However, this can only be used with corresponding support in the host kernel - which was dropped years ago (in c17b98cf "KVM: PPC: Book3S HV: Remove code for PPC970 processors" of 2014-12-03 to be precise). Therefore it should be ok to drop this immediately. Just to be clear this only affects *KVM HV* guests with PowerPC 970, and those already require an ancient host kernel. TCG and KVM PR guests with PowerPC 970 should still work. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Thomas Huth <thuth@redhat.com>
* target/ppc: add basic support for PTCR on POWER9Cédric Le Goater2018-05-047-0/+71
| | | | | | | | | | The Partition Table Control Register (PTCR) is a hypervisor privileged SPR. It contains the host real address of the Partition Table and its size. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: return a nil HPT base address on sPAPR machinesCédric Le Goater2018-05-041-0/+3
| | | | | | | | | | | | | commit e57ca75ce3b2 ("target/ppc: Manage external HPT via virtual hypervisor") exported a set of methods to manipulate the HPT from the core hash MMU. But SPR_SDR1 is still used under some circumstances to get the base address of the HPT, which is incorrect for the sPAPR machines. Only the logging should be impacted. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180502' into stagingPeter Maydell2018-05-038-106/+150
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Queued TCG patches # gpg: Signature made Wed 02 May 2018 18:43:33 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20180502: tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st tcg: Improve TCGv_ptr support tcg: Allow wider vectors for cmp and mul tcg/arm: Fix memory barrier encoding tcg: Document INDEX_mul[us]h_* Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg: workaround branch instruction overflow in tcg_out_qemu_ld/stLaurent Vivier2018-05-013-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st slow path. BC instruction uses a relative address encoded on 14 bits. The slow path functions are added at the end of the generated instructions buffer, in the reverse order of the callers. So more we have slow path functions more the distance between the caller (BC) and the function increases. This patch changes the behavior to generate the functions in the same order of the callers. Cc: qemu-stable@nongnu.org Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20180429235840.16659-1-lvivier@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Improve TCGv_ptr supportRichard Henderson2018-05-014-94/+130
| | | | | | | | | | | | | | | | | | | | | | | | Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Allow wider vectors for cmp and mulRichard Henderson2018-05-011-4/+4
| | | | | | | | | | | | | | | | | | In db432672, we allow wide inputs for operations such as add. However, in 212be173 and 3774030a we didn't do the same for compare and multiply. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/arm: Fix memory barrier encodingHenry Wertz2018-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Henry Wertz <hwertz10@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Document INDEX_mul[us]h_*Richard Henderson2018-05-011-0/+8
| | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into stagingPeter Maydell2018-05-032-0/+7
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Just one trace # gpg: Signature made Wed 02 May 2018 07:59:38 BST # gpg: using RSA key 71D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" # gpg: aka "[jpeg image of size 3330]" # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz/tags/for-upstream: 9p: add trace event for v9fs_setattr() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * 9p: add trace event for v9fs_setattr()Greg Kurz2018-05-022-0/+7
|/ | | | | | | | Don't print the tv_nsec part of atime and mtime, to stay below the 10 argument limit of trace events. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* Merge remote-tracking branch ↵Peter Maydell2018-05-013-33/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier/tags/m68k-for-2.13-pull-request' into staging # gpg: Signature made Tue 01 May 2018 14:53:58 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.13-pull-request: hw/m68k/mcf5208: Fix trivial typo in board description m68k: remove dead code (Coverity CID1390617) m68k: Fix floatx80_lognp1 (Coverity CID1390587) m68k: fix subx mem, mem instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/m68k/mcf5208: Fix trivial typo in board descriptionThomas Huth2018-05-011-1/+1
| | | | | | | | | | | | | | | | | | It's the MCF5208 evaluation board, not the MCF5206 eval board. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180429094002.3293c9de@thl530.multi.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * m68k: remove dead code (Coverity CID1390617)Laurent Vivier2018-05-011-29/+14
| | | | | | | | | | | | | | | | | | | | floatx80_sin() and floatx80_cos() are derived from one sincos() function. They have both unused code coming from their common origin. Remove it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430170156.1860-2-laurent@vivier.eu>
| * m68k: Fix floatx80_lognp1 (Coverity CID1390587)Laurent Vivier2018-05-011-1/+2
| | | | | | | | | | | | | | | | | | | | return the result of packFloatx80() instead of dropping it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180430170156.1860-1-laurent@vivier.eu>
| * m68k: fix subx mem, mem instructionPavel Dovgalyuk2018-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patch fixes decrement of the pointers for subx mem, mem instructions. Without the patch pointers are decremented by OS_* constant value instead of retrieving the corresponding data size and using it as a decrement. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180418064152.24606.71975.stgit@pasha-VirtualBox> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch ↵Peter Maydell2018-04-302-5/+10
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream' into staging edgar/xilinx-next-2018-01.for-upstream # gpg: Signature made Mon 30 Apr 2018 15:52:35 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream: target-microblaze: mmu: Make the TLBX MISS bit read-only target-microblaze: mmu: Make TLBSX write-only target-microblaze: Don't clobber the IMM reg for ld/st reversed target-microblaze: Fix trap checks for FPU insns target-microblaze: Respect MSR.PVR as read-only Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-microblaze: mmu: Make the TLBX MISS bit read-onlyEdgar E. Iglesias2018-04-301-0/+4
| | | | | | | | | | | | | | | | Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Make TLBSX write-onlyEdgar E. Iglesias2018-04-301-1/+4
| | | | | | | | | | | | | | | | Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Don't clobber the IMM reg for ld/st reversedEdgar E. Iglesias2018-04-301-2/+0
| | | | | | | | | | | | | | Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Fix trap checks for FPU insnsEdgar E. Iglesias2018-04-301-1/+1
| | | | | | | | | | | | | | | | Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Respect MSR.PVR as read-onlyEdgar E. Iglesias2018-04-301-1/+1
| | | | | | | | | | | | | | Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* | Merge remote-tracking branch ↵Peter Maydell2018-04-3071-10882/+11888
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/linux-user-for-2.13-pull-request' into staging # gpg: Signature made Mon 30 Apr 2018 10:05:56 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-2.13-pull-request: (42 commits) linux-user: Add ARM get_tls syscall support linux-user: move xtensa cpu loop to xtensa directory linux-user: move hppa cpu loop to hppa directory linux-user: move riscv cpu loop to riscv directory linux-user: move tilegx cpu loop to tilegx directory linux-user: move s390x cpu loop to s390x directory linux-user: move alpha cpu loop to alpha directory linux-user: move m68k cpu loop to m68k directory linux-user: move microblaze cpu loop to microblaze directory linux-user: move cris cpu loop to cris directory linux-user: move sh4 cpu loop to sh4 directory linux-user: move openrisc cpu loop to openrisc directory linux-user: move nios2 cpu loop to nios2 directory linux-user: move mips/mips64 cpu loop to mips directory linux-user: move ppc/ppc64 cpu loop to ppc directory linux-user: move sparc/sparc64 cpu loop to sparc directory linux-user: move arm cpu loop to arm directory linux-user: move aarch64 cpu loop to aarch64 directory linux-user: move i386/x86_64 cpu loop to i386 directory linux-user: create a dummy per arch cpu_loop.c ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * linux-user: Add ARM get_tls syscall supportChristophe Lyon2018-04-302-0/+4
| | | | | | | | | | | | | | | | | | Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180416091845.7315-1-christophe.lyon@st.com> [lv: moved the change to linux-user/arm/cpu_loop.c] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: move xtensa cpu loop to xtensa directoryLaurent Vivier2018-04-302-250/+241
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to xtensa/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-20-laurent@vivier.eu>
| * linux-user: move hppa cpu loop to hppa directoryLaurent Vivier2018-04-302-193/+186
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to hppa/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-19-laurent@vivier.eu>
| * linux-user: move riscv cpu loop to riscv directoryLaurent Vivier2018-04-302-100/+93
| | | | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to riscv/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-18-laurent@vivier.eu>
| * linux-user: move tilegx cpu loop to tilegx directoryLaurent Vivier2018-04-302-267/+260
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to tilegx/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-17-laurent@vivier.eu>
| * linux-user: move s390x cpu loop to s390x directoryLaurent Vivier2018-04-302-146/+139
| | | | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to s390x/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-16-laurent@vivier.eu>
| * linux-user: move alpha cpu loop to alpha directoryLaurent Vivier2018-04-302-204/+199
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to alpha/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-15-laurent@vivier.eu>
| * linux-user: move m68k cpu loop to m68k directoryLaurent Vivier2018-04-302-149/+145
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to m68k/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-14-laurent@vivier.eu>
| * linux-user: move microblaze cpu loop to microblaze directoryLaurent Vivier2018-04-302-155/+150
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to microblaze/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-13-laurent@vivier.eu>
| * linux-user: move cris cpu loop to cris directoryLaurent Vivier2018-04-302-90/+89
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to cris/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-12-laurent@vivier.eu>
| * linux-user: move sh4 cpu loop to sh4 directoryLaurent Vivier2018-04-302-90/+85
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to sh4/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-11-laurent@vivier.eu>
| * linux-user: move openrisc cpu loop to openrisc directoryLaurent Vivier2018-04-302-96/+89
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to openrisc/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-10-laurent@vivier.eu>
| * linux-user: move nios2 cpu loop to nios2 directoryLaurent Vivier2018-04-302-133/+126
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to nios2/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-9-laurent@vivier.eu>
| * linux-user: move mips/mips64 cpu loop to mips directoryLaurent Vivier2018-04-303-732/+724
| | | | | | | | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to mips/cpu_loop.c. Include mips/cpu_loop.c in mips64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-8-laurent@vivier.eu>
| * linux-user: move ppc/ppc64 cpu loop to ppc directoryLaurent Vivier2018-04-302-559/+554
| | | | | | | | | | | | | | | | | | No code change, only move code from main.c to ppc/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-7-laurent@vivier.eu>
| * linux-user: move sparc/sparc64 cpu loop to sparc directoryLaurent Vivier2018-04-303-294/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to sparc/cpu_loop.c. Include sparc/cpu_loop.c in sparc64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-6-laurent@vivier.eu>
| * linux-user: move arm cpu loop to arm directoryLaurent Vivier2018-04-302-431/+432
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to arm/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-5-laurent@vivier.eu>
| * linux-user: move aarch64 cpu loop to aarch64 directoryLaurent Vivier2018-04-302-107/+158
| | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to aarch64/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-4-laurent@vivier.eu>
| * linux-user: move i386/x86_64 cpu loop to i386 directoryLaurent Vivier2018-04-303-354/+345
| | | | | | | | | | | | | | | | | | | | | | | | No code change, only move code from main.c to i386/cpu_loop.c. Include i386/cpu_loop.c in x86_64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-3-laurent@vivier.eu>
| * linux-user: create a dummy per arch cpu_loop.cLaurent Vivier2018-04-3024-15/+588
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a cpu_loop-common.h for future use by these new files and use it in the existing main.c Introduce target_cpu_copy_regs(): declare the function in cpu_loop-common.h and an empty function for each target, to move all the cpu_loop prologues to this function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-2-laurent@vivier.eu>
| * linux-user: define TARGET_ARCH_HAS_SETUP_FRAMELaurent Vivier2018-04-3023-110/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling setup_frame() conditionally to a list of known targets, define TARGET_ARCH_HAS_SETUP_FRAME if the target provides the function and call it only if the macro is defined. Move declarations of setup_frame() and setup_rt_frame() to linux-user/signal-common.h Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-21-laurent@vivier.eu>