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| * | hw/s390x/sclp: Use address_space_memory_is_io() in sclp_service_call()Philippe Mathieu-Daudé2025-10-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cpu_address_space_init() isn't called during vCPU creation, its single address space is the global &address_space_memory. As s390x boards don't call cpu_address_space_init(), cpu->as points to &address_space_memory. We can then replace cpu_physical_memory_is_io() by the semantically equivalent address_space_memory_is_io() call. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20251002084203.63899-5-philmd@linaro.org>
| * | target/i386/arch_memory_mapping: Use address_space_memory_is_io()Philippe Mathieu-Daudé2025-10-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all functions have an address space argument, it is trivial to replace cpu_physical_memory_is_io() by address_space_memory_is_io(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-4-philmd@linaro.org>
| * | system/memory: Factor address_space_is_io() outPhilippe Mathieu-Daudé2025-10-072-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Factor address_space_is_io() out of cpu_physical_memory_is_io(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-3-philmd@linaro.org>
| * | docs/devel/loads-stores: Stop mentioning cpu_physical_memory_write_rom()Philippe Mathieu-Daudé2025-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the documentation after commit 3c8133f9737 ("Rename cpu_physical_memory_write_rom() to address_space_write_rom()"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-2-philmd@linaro.org>
| * | system/memory: Split address_space_write_rom_internalRichard Henderson2025-10-071-45/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 2dbaf58bbe7 we conditionally skipped the increment of buf because ubsan warns incrementing NULL, and buf is always NULL for FLUSH_CACHE. However, the existence of the test for NULL caused Coverity to warn that the memcpy in the WRITE_DATA case lacked a test for NULL. Duplicate address_space_write_rom_internal into the two callers, dropping enum write_rom_type, and simplify. This eliminates buf in the flush case, and eliminates the conditional increment of buf in the write case. Coverity: CID 1621220 Fixes: 2dbaf58bbe7 ("system/physmem: Silence warning from ubsan") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250922192940.2908002-1-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | system/ramblock: Move RAMBlock helpers out of "system/ram_addr.h"Philippe Mathieu-Daudé2025-10-072-11/+11
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-6-philmd@linaro.org>
| * | system/ramblock: Rename @start -> @offset in ram_block_discard_range()Philippe Mathieu-Daudé2025-10-072-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename @start as @offset, since it express an offset within a RAMBlock. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-5-philmd@linaro.org>
| * | system/ramblock: Move ram_block_discard_*_range() declarationsPhilippe Mathieu-Daudé2025-10-076-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keep RAM blocks API in the same header: "system/ramblock.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-4-philmd@linaro.org>
| * | system/ramblock: Move ram_block_is_pmem() declarationPhilippe Mathieu-Daudé2025-10-074-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move ramblock_is_pmem() along with the RAM Block API exposed by the "system/ramblock.h" header. Rename as ram_block_is_pmem() to keep API prefix consistency. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-3-philmd@linaro.org>
| * | system/ramblock: Remove obsolete commentPhilippe Mathieu-Daudé2025-10-071-5/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This comment was added almost 5 years ago in commit 41aa4e9fd84 ("ram_addr: Split RAMBlock definition"). Clearly it got ignored: $ git grep -l system/ramblock.h hw/display/virtio-gpu-udmabuf.c hw/hyperv/hv-balloon.c hw/virtio/vhost-user.c migration/dirtyrate.c migration/file.c migration/multifd-nocomp.c migration/multifd-qatzip.c migration/multifd-qpl.c migration/multifd-uadk.c migration/multifd-zero-page.c migration/multifd-zlib.c migration/multifd-zstd.c migration/multifd.c migration/postcopy-ram.c system/ram-block-attributes.c target/i386/kvm/tdx.c tests/qtest/fuzz/generic_fuzz.c At this point it seems saner to just remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-2-philmd@linaro.org>
* | Merge tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu into ↵Richard Henderson2025-10-0723-1731/+3222
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * target/arm: Don't set HCR.RW for AArch32 only CPUs * new board model: amd-versal2-virt * xlnx-zynqmp: model the GIC for the Cortex-R5 RPU cluster * hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header * Emulate FEAT_RME_GPC2 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmjlH0AZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gvaD/92LoDOIPQYCw72nwr/hiC8 # DAJddqKL1VvirtcrTuwytB1+w/tM2FdNx4ADzryHiNEDay2gXl0g4X4Pq6QFwu8B # u2gxQhZZc1XWJgvX06CDJZPIUoazQgri21359c+9mJrI94igq1Gisj+KJ2gaMJ/J # hrtsbovKuuKwMyCwCSK0hqvrUFyechfvJ0MzwVXyHn80lvSeYVbHf8ahdM72Lqdt # PFJuM6hM/bBbclMRrcgRZJ3gi6HGHdKQ+LyYeQkvpHtaO3FWBgyJE7dtzs3mj4c9 # zw7kFJi56/19G6Fx3CESCIjoUQxLPZ1wDljqcQ9+mIwhQ4Dm7cy/D5z018TotIws # mNLpMyEYiyC6dl1TxaJkha9jB6MB+nlglpbOGyRDYD1xwV8o5lidAahKxtmZUrGp # sErUqCL5f+e/inwkFLxKrA2Hk1mjFDzf9/aEF/CyA30JYzRrhCfMoffiqtpPpU5D # +OD1OAnj+W7HSBzO6N2I+4bfsaILw61YvckaBbO9+Br9yx8QseXHwXGh+RgsMhY4 # yJdde//tRusT32SAVoQKCMTJM5Rkrt4wu1D0F4LFL/4rJaqkAhqirNP4v5JEjrlk # UDNa19E1TfmLbCG0TfQBWd3kwLYizqjTO0006jpTMX+KIu5aInEIHzzVrKEKK4t5 # fCw9fUM8T4fSTV71wJ/28Q== # =jFB3 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Oct 2025 07:10:08 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu: (62 commits) target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme target/arm: Implement APPSAA target/arm: Fix GPT fault type for address outside PPS target/arm: Implement SPAD, NSPAD, RLPAD target/arm: Implement GPT_NonSecureOnly target/arm: GPT_Secure is reserved without FEAT_SEL2 target/arm: Add cur_space to S1Translate target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write target/arm: Add GPCCR fields from ARM revision L.b target/arm: Add isar feature test for FEAT_RME_GPC2 hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 hw/arm/xlnx-zynqmp: introduce helper to compute RPU number hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header tests/functional/test_aarch64_xlnx_versal: test the versal2 machine hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine docs/system/arm/xlnx-versal-virt: add a note about dumpdtb docs/system/arm/xlnx-versal-virt: update supported devices hw/arm/xlnx-versal-virt: tidy up hw/arm/xlnx-versal-virt: split into base/concrete classes ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rmeRichard Henderson2025-10-072-1/+3
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement APPSAARichard Henderson2025-10-071-1/+2
| | | | | | | | | | | | | | | | | | This bit allows all spaces to access memory above PPS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix GPT fault type for address outside PPSRichard Henderson2025-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | The GPT address size fault is for the table itself. The physical address being checked gets Granule protection fault at Level 0 (R_JFFHB). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement SPAD, NSPAD, RLPADRichard Henderson2025-10-071-2/+21
| | | | | | | | | | | | | | | | | | These bits disable all access to a particular address space. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement GPT_NonSecureOnlyRichard Henderson2025-10-071-1/+9
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: GPT_Secure is reserved without FEAT_SEL2Richard Henderson2025-10-071-4/+8
| | | | | | | | | | | | | | | | | | For GPT_Secure, if SEL2 is not enabled, raise a GPCF_Walk exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add cur_space to S1TranslateRichard Henderson2025-10-071-18/+19
| | | | | | | | | | | | | | | | | | | | | | We've been updating in_space and then using hacks to access the original space. Instead, update cur_space and leave in_space unchanged. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Enable FEAT_RME_GPC2 bits in gpccr_writeRichard Henderson2025-10-071-0/+5
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add GPCCR fields from ARM revision L.bRichard Henderson2025-10-071-0/+6
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add isar feature test for FEAT_RME_GPC2Richard Henderson2025-10-071-0/+5
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé2025-10-073-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | When removing the spitz and tosa board, commit b62151489ae ("hw/arm: Remove deprecated akita, borzoi spitz, terrier, tosa boards") removed the last calls to sl_bootparam_write(). Remove it, along with the "hw/arm/sharpsl.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20251001084047.67423-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2025-10-072-1/+80
| | | | | | | | | | | | | | | | | | | | This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Clément Chigot <chigot@adacore.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-4-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-zynqmp: introduce helper to compute RPU numberClément Chigot2025-10-071-3/+12
| | | | | | | | | | | | | | | | | | | | This helper will avoid repeating the MIN/MAX formula everytime the number of RPUs available is requested. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-3-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2025-10-072-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | This define will be needed in a later patch in XlnxZynqMPState structure, hence move it within xlnx-zynqmp header. Add XLXN_ZYNQMP prefix as it's now public. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-2-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/functional/test_aarch64_xlnx_versal: test the versal2 machineLuc Michel2025-10-071-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a test for the amd-versal2-virt machine using the same command line, kernel, initrd than the ones used for amd-versal-virt. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-48-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machineLuc Michel2025-10-072-10/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Versal Gen 2 Virtual development machine embedding a versal2 SoC. This machine follows the same principle than the xlnx-versal-virt machine. It creates its own DTB and feeds it to the software payload. This way only implemented devices are exposed to the guest and the user does not need to provide a DTB. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-47-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * docs/system/arm/xlnx-versal-virt: add a note about dumpdtbLuc Michel2025-10-071-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add a note in the DTB section explaining how to dump the generated DTB using the dumpdtb machine option. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-46-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * docs/system/arm/xlnx-versal-virt: update supported devicesLuc Michel2025-10-071-2/+5
| | | | | | | | | | | | | | | | | | | | | | Update the list of supported devices in the Versal SoCs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-45-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal-virt: tidy upLuc Michel2025-10-071-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove now unused clock nodes. They have been replaced by the ones created in the SoC. Remove the unused cfg.secure VersalVirt field. Remove unecessary include directives. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-44-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal-virt: split into base/concrete classesLuc Michel2025-10-071-22/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the xlnx-versal-virt machine type into a base abstract type and a concrete type. There is no functional change. This is in preparation for the versal2 machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-43-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virtLuc Michel2025-10-073-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-42-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add versal2 SoCLuc Michel2025-10-072-15/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Versal Gen 2 (versal2) version of the Versal SoC family. This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters) and 10 Cortex-R52 cores (split into 5 clusters). The similarities between versal and versal2 in term of architecture allow to reuse the VersalMap structure to almost fully describe the implemented parts of versal2. The versal2 eFuse device differs quite a lot from the versal one and is left as future work. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-41-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/tcg/cpu64: add the cortex-a78ae CPULuc Michel2025-10-071-0/+78
| | | | | | | | | | | | | | | | | | | | | | Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-40-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add the target field in IRQ descriptorLuc Michel2025-10-071-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the target field in the IRQ descriptor. This allows to target an IRQ to another IRQ controller than the GIC(s). Other supported targets are the PMC PPU1 CPU interrupt controller and the EAM (Error management) device. Those two devices are currently not implemented so IRQs targeting those will be left unconnected. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-39-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMapLuc Michel2025-10-071-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the per_cluster_gic switch to the VersalCpuClusterMap structure. When set, this indicates that a GIC instance should by created per-cluster instead of globally for the whole RPU or APU. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-38-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel2025-10-073-0/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-37-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: tidy upLuc Michel2025-10-072-225/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove now unused macros in xlnx-versal.[ch]. Those macros have been replaced by the VersalMap structure that serves as a central description for the SoC. The ones still in use in the versal_unimp function are inlined. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-36-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2025-10-072-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the bsa.h header for ARM timer and maintainance IRQ indices instead of redefining our owns. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-35-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: reconnect the CRL to the other devicesLuc Michel2025-10-071-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CRL connects to various devices through link properties to be able to reset them. The connections were dropped during the SoC refactoring. Reintroduce them now. Rely on the QOM tree to retrieve the devices to connect. The component parts of the device names are chosen to match the properties on the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-34-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2025-10-072-79/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the device reset logic to have a common register write callback for all the devices. This uses a decode function to map the register address to the actual peripheral to reset. This refactoring changes the CPU property name from cpu_r5[*] to rpu[*] to ease with the connections in the Versal SoC. It also fixes a bug where the gem device pointer was mapped to the usb link property. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-33-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2025-10-072-21/+58
| | | | | | | | | | | | | | | | | | | | | | | | Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-32-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc/xlnx-versal-crl: remove unnecessary include directivesLuc Michel2025-10-071-4/+1
| | | | | | | | | | | | | | | | | | | | | | Drop unused include directives from xlnx-versal-crl.c Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-31-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel2025-10-073-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the number of CPUs in the SoC. Use it in the xlnx-versal-virt machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-30-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: ddr: refactor creationLuc Michel2025-10-073-106/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-29-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2025-10-072-8/+16
| | | | | | | | | | | | | | | | | | | | | | Refactor the OCM creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-28-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: rpu: refactor creationLuc Michel2025-10-073-46/+26
| | | | | | | | | | | | | | | | | | | | | | | | Refactor the RPU cluster creation using the VersalMap structure. This effectively instantiate the RPU GICv2 which was not instantiated before. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-27-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add support for GICv2Luc Michel2025-10-071-20/+62
| | | | | | | | | | | | | | | | | | | | | | | | Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-26-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2025-10-072-4/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-25-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias2025-10-074-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a 'first-cpu-index' property for specifying the first QEMU CPU connected to the GICv3. This makes it possible to have multiple instances of the GICv3 connected to different CPU clusters. For KVM, mark this property has unsupported. It probably does not make much sense as it is intented to be used to model non-SMP systems. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-24-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>