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path: root/bsd-user/riscv/target_arch_cpu.h (follow)
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* bsd-user, linux-user: introduce qemu_process_cpu_eventsPaolo Bonzini2025-09-171-1/+1
| | | | | | | | | Add a user-mode emulation version of the function. More will be added later, for now it is just process_queued_cpu_work. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* user: Declare cpu_loop() once in 'user/cpu_loop.h'Philippe Mathieu-Daudé2024-12-201-1/+1
| | | | | | | | | | Declare cpu_loop() once in "user/cpu_loop.h". bsd-user gets the G_NORETURN attribute. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-18-philmd@linaro.org>
* bsd-user: Implement RISC-V CPU register cloning and reset functionsMark Corbin2024-10-021-0/+14
| | | | | | | | | | | Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* bsd-user: Add RISC-V CPU execution loop and syscall handlingMark Corbin2024-10-021-0/+94
| | | | | | | | | | | | | | | Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-3-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* bsd-user: Implement RISC-V CPU initialization and main loopMark Corbin2024-10-021-0/+40
Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>