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path: root/hw/pci-bridge/cxl_downstream.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* hw/pci-bridge: Constify all PropertyRichard Henderson2024-12-151-1/+1
* hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.Jonathan Cameron2024-11-041-13/+10
* hw: Use device_class_set_legacy_reset() instead of opencodingPeter Maydell2024-09-131-1/+1
* hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron2024-02-141-2/+2
* hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron2023-11-071-0/+14
* hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron2023-11-071-3/+1
* hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron2023-11-071-1/+1
* hw/pci: spelling fixesMichael Tokarev2023-09-201-1/+1
* hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron2023-03-021-1/+1
* pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov2022-12-211-1/+0
* pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron2022-06-161-0/+249