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* Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson2024-04-251-2/+1
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| * hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return booleanZhao Liu2024-04-251-2/+1
* | hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell2024-04-252-3/+3
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* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ...Peter Maydell2024-03-131-1/+1
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| * hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu2024-03-121-0/+1
| * hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.Jonathan Cameron2024-03-121-1/+1
* | bulk: Access existing variables initialized to &S->F when availablePhilippe Mathieu-Daudé2024-03-121-1/+1
* | hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu2024-03-121-0/+1
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* hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth2024-03-091-4/+4
* hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron2024-02-143-6/+6
* hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handlingJonathan Cameron2024-02-141-6/+0
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell2024-01-041-2/+0
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| * meson: remove CONFIG_ALLPaolo Bonzini2023-12-311-2/+0
* | hw/pci-bridge: Constify VMStateRichard Henderson2023-12-307-7/+7
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* hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron2023-11-071-0/+14
* hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron2023-11-071-3/+1
* hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron2023-11-071-10/+1
* hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron2023-11-073-3/+3
* hw/pci-bridge/cxl-upstream: Add serial number extended capability supportJonathan Cameron2023-10-041-2/+13
* hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBISDave Jiang2023-09-211-1/+1
* hw/pci: spelling fixesMichael Tokarev2023-09-202-2/+2
* hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()Peter Maydell2023-08-031-4/+1
* meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé2023-06-201-2/+2
* hw/pci-bridge: make building pcie-to-pci bridge configurableSebastian Ott2023-05-192-1/+7
* hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron2023-05-191-0/+3
* hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEVJonathan Cameron2023-04-241-40/+19
* hw/pci-bridge: pci_expander_bridge fix type in pxb_cxl_dev_reset()Jonathan Cameron2023-04-241-1/+1
* hw/pxb-cxl: Support passthrough HDM Decoders unless overriddenJonathan Cameron2023-03-071-5/+39
* hw/pci-bridge/cxl_root_port: Wire up MSIJonathan Cameron2023-03-071-0/+61
* hw/pci-bridge/cxl_root_port: Wire up AERJonathan Cameron2023-03-071-0/+3
* hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron2023-03-021-1/+1
* hw: Move ich9.h to southbridge/Bernhard Beschow2023-02-271-1/+1
* pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-capIgor Mammedov2023-01-281-1/+6
* pci_bridge: remove whitespaceIgor Mammedov2023-01-281-1/+0
* bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé2023-01-181-1/+1
* include/hw/cxl: Move typedef PXBDev to cxl.h, and put it to useMarkus Armbruster2023-01-081-1/+0
* include/hw/pci: Break inclusion loop pci_bridge.h and cxl.hMarkus Armbruster2023-01-081-1/+1
* pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov2022-12-219-9/+0
* remove DEC 21154 PCI bridgeIgor Mammedov2022-12-213-175/+0
* pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell2022-12-161-5/+9
* pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell2022-12-161-3/+5
* hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron2022-11-071-1/+194
* pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron2022-06-162-1/+250
* pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron2022-06-162-1/+217
* pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron2022-06-093-13/+38
* hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron2022-06-091-1/+1
* CXL/cxl_component: Add cxl_get_hb_cstate()Jonathan Cameron2022-05-131-0/+7
* acpi/cxl: Create the CEDT (9.14.1)Ben Widawsky2022-05-131-17/+0
* hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)Ben Widawsky2022-05-131-7/+59
* hw/cxl/rp: Add a root portBen Widawsky2022-05-134-1/+247