| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions | Bin Meng | 2020-06-19 | 1 | -15/+14 |
| * | riscv/opentitan: Connect the UART device | Alistair Francis | 2020-06-19 | 1 | -2/+23 |
| * | riscv/opentitan: Connect the PLIC device | Alistair Francis | 2020-06-19 | 1 | -2/+12 |
| * | riscv/opentitan: Fix the ROM size | Alistair Francis | 2020-06-19 | 1 | -1/+2 |
| * | qdev: Convert bus-less devices to qdev_realize() with Coccinelle | Markus Armbruster | 2020-06-15 | 1 | -2/+1 |
| * | sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 | Markus Armbruster | 2020-06-15 | 1 | -4/+2 |
| * | qom: Less verbose object_initialize_child() | Markus Armbruster | 2020-06-15 | 1 | -2/+1 |
| * | riscv: Fix to put "riscv.hart_array" devices on sysbus | Markus Armbruster | 2020-06-15 | 1 | -3/+2 |
| * | riscv: Initial commit of OpenTitan machine | Alistair Francis | 2020-06-03 | 1 | -0/+184 |