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* hw/riscv: opentitan: Fixup local variables shadowingAlistair Francis2023-09-291-1/+1
* hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé2023-06-131-1/+2
* hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé2023-06-131-3/+7
* hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé2023-06-131-1/+1
* hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé2023-06-131-12/+9
* hw/riscv/opentitan: Rename machine_[class]_init() functionsPhilippe Mathieu-Daudé2023-06-131-4/+4
* *: Add missing includes of qemu/error-report.hRichard Henderson2023-03-221-0/+1
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa2023-02-071-40/+40
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng2023-01-061-2/+0
* hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa2023-01-061-0/+3
* hw/riscv/opentitan: bump opentitanWilfred Mallawa2023-01-061-8/+13
* hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis2022-09-271-1/+7
* hw/riscv: opentitan: Fixup resetvecAlistair Francis2022-09-271-1/+1
* hw/riscv: opentitan: bump opentitan versionWilfred Mallawa2022-09-071-4/+8
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-1/+1
* riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa2022-04-221-4/+32
* hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa2022-03-031-3/+9
* riscv: opentitan: fixup plic stride lenWilfred Mallawa2022-01-211-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis2021-10-281-2/+2
* hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-5/+17
* hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
* hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-0/+3
* hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-0/+8
* hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-151-0/+6
* hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-151-0/+3
* hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis2021-06-241-3/+11
* hw/riscv: Fix OT IBEX reset vectorAlexander Wagner2021-05-111-1/+1
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-4/+4
* Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-021-1/+0
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-171-24/+57
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-1/+2
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-091-0/+1
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-42/+42
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-5/+2
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-101-4/+2
* hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-15/+14
* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-2/+23
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-2/+12
* riscv/opentitan: Fix the ROM sizeAlistair Francis2020-06-191-1/+2
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-2/+1
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-151-4/+2
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-2/+1
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-3/+2