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path: root/hw/riscv/spike.c (follow)
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* target/riscv: support new isa extension detection devicetree propertiesConor Dooley2024-02-091-4/+2
* hw/riscv: Validate cluster and NUMA node boundaryGavin Shan2023-06-261-0/+2
* hw/riscv: Add signature dump function for spike to run ACT testsWeiwei Li2023-05-051-0/+13
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-10/+1
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza2023-02-071-1/+2
* hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza2023-02-071-3/+3
* hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza2023-02-071-9/+9
* hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza2023-01-201-1/+1
* hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza2023-01-201-3/+3
* hw/riscv/spike.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-3/+1
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza2023-01-201-4/+5
* hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-201-8/+2
* hw/riscv/spike.c: load initrd right after riscv_load_kernel()Daniel Henrique Barboza2023-01-201-16/+15
* hw/riscv/spike: use 'fdt' from MachineStateDaniel Henrique Barboza2023-01-201-7/+5
* hw/riscv: spike: Decouple create_fdt() dependency to ELF loadingBin Meng2023-01-201-10/+51
* hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza2023-01-201-9/+5
* hw/riscv: spike: Remove the out-of-date commentsBin Meng2023-01-201-5/+0
* hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng2023-01-201-2/+1
* hw/char: riscv_htif: Drop useless assignment of memory regionBin Meng2023-01-201-3/+2
* hw/riscv: spike: Remove misleading commentsBin Meng2023-01-061-1/+0
* hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza2022-10-171-0/+6
* hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza2022-09-071-1/+1
* hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI2022-05-241-1/+1
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng2022-04-291-2/+3
* hw/riscv: Remove macros for ELF BIOS image namesAnup Patel2022-01-211-2/+2
* hw/riscv: spike: Allow using binary firmware as biosAnup Patel2022-01-211-16/+25
* hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-211-5/+9
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-211-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0
* qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-171-4/+4
* hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-171-21/+24
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-171-1/+2
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-171-1/+1
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-3/+8
* hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-091-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-091-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-091-1/+2
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-74/+158
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1