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* | intel_iommu: Add a placeholder variable for scalable mode stage-1 translationZhenzhong Duan2025-01-151-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an new element flts in IntelIOMMUState to mark stage-1 translation support in scalable mode, this element will be exposed as an intel_iommu property x-flts finally. For now, it's only a placehholder and used for address width compatibility check and block host device passthrough until nesting is supported. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | intel_iommu: Make pasid entry type check accurateZhenzhong Duan2025-01-151-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-3-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | intel_iommu: Use the latest fault reasons defined by specYu Zhang2025-01-152-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spec revision 3.0 or above defines more detailed fault reasons for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Note spec revision has no relation with VERSION register, Guest kernel should not use that register to judge what features are supported. Instead cap/ecap bits should be checked. Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-2-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | cpuhp: make sure that remove events are handled within the same SCIIgor Mammedov2025-01-151-9/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU_SCAN_METHOD was processing insert events first and only if insert event was not present then it would check remove event. Normally it's not an issue as it doesn't make much sense tho hotplug and immediately unplug it. In this corner case, which can be reproduced with: qemu -smp 1,maxcpus=2 -cpu host -monitor stdio \ -drive if=pflash,format=raw,readonly,file=edk2-x86_64-code.fd * boot till GRUB prompt and pause guest (either via monitor or stop GRUB from automatic boot) * at monitor prompt add CPU: device_add host-x86_64-cpu,socket-id=0,core-id=1,thread-id=0,id=foo * let guest OS boot completely, and unplug CPU from monitor prompt: device_del foo which triggers GPE event that leads to CPU_SCAN_METHOD on guest side as result of above cpu 'foo' will not be hotunplugged, since QEMU sees insert event and ignores remove event (leaving it in pending state) for the GPE event. Any follow up CPU hotplug/unplug action from QEMU side will handle previously ignored event, so as workaround user can repeat device_del. Fix this corner-case by queuing remove events independently from insert events, aka the same way as we do with insert events. And then go over remove queue to send eject notify events to OSPM within the same GPE event. PS: Process remove queue after the cpu add queue has been processed 1st to ensure that OSPM gets hotadd evets after hotremove ones. PS2: Case where it's still borken happens when guest OS is Linux and device_del happens before guest OS initializes ACPI subsystem. Culprit in this case though is the guest kernel, which mangles GPE.sts (by clearing them up) and thus pending SCI turns to NOP leaving insert/remove events in pending state. That is the guest bug and should be fixed there. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reported-by: Eric Mackay <eric.mackay@oracle.com> Message-Id: <20241210163945.3422623-3-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | pci: ensure valid link status bits for downstream portsSebastian Ott2025-01-151-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport 0000:08:01.0: pciehp: Slot(2): Card present pcieport 0000:08:01.0: pciehp: Slot(2): Link Up pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000 There's 2 cases where LNKSTA isn't setup properly: * the downstream device has no express capability * max link width of the bridge is 0 Move the sanity checks added via 88c869198aa63 ("pci: Sanity test minimum downstream LNKSTA") outside of the branch to make sure downstream ports always have a valid LNKSTA. Signed-off-by: Sebastian Ott <sebott@redhat.com> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-Id: <20241203121928.14861-1-sebott@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | virtio-gpu: Add definition for resource_uuid featureDorinda Bassey2025-01-152-0/+11
|/ | | | | | | | | | Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment of resources UUIDs for export to other virtio devices. Signed-off-by: Dorinda Bassey <dbassey@redhat.com> Message-Id: <20241007070013.3350752-1-dbassey@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/tricore/triboard: Remove unnecessary use of &first_cpuPhilippe Mathieu-Daudé2025-01-131-4/+2
| | | | | | | | | | | | | | | | | | | | triboard_machine_init() has access to the single CPU via: TriBoardMachineState { TC27XSoCState { TriCoreCPU cpu; ... } tc27x_soc; } ms; Pass it as argument to tricore_load_kernel() so we can remove the &first_cpu global use. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20250110180909.83165-1-philmd@linaro.org>
* hw/usb/hcd-xhci-pci: Use event ring 0 if mapping unsupportedPhil Dennis-Jordan2025-01-131-0/+4
| | | | | | | | | | | | | | | | | The XHCI specification, section 4.17.1 specifies that "If the Number of Interrupters (MaxIntrs) field is greater than 1, then Interrupter Mapping shall be supported." and "If Interrupter Mapping is not supported, the Interrupter Target field shall be ignored by the xHC and all Events targeted at Interrupter 0." QEMU's XHCI device has so far not specially addressed this case, so we add a check to xhci_event() to redirect to event ring and interrupt 0 if mapping is disabled. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241227121336.25838-4-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/usb/hcd-xhci-pci: Use modulo to select MSI vector as per specPhil Dennis-Jordan2025-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU would crash with a failed assertion if the XHCI controller attempted to raise the interrupt on an interrupter corresponding to a MSI vector with a higher index than the highest configured for the device by the guest driver. This behaviour is correct on the MSI/PCI side: per PCI 3.0 spec, devices must ensure they do not send MSI notifications for vectors beyond the range of those allocated by the system/driver software. Unlike MSI-X, there is no generic way for handling aliasing in the case of fewer allocated vectors than requested, so the specifics are up to device implementors. (Section 6.8.3.4. "Sending Messages") It turns out the XHCI spec (Implementation Note in section 4.17, "Interrupters") requires that the host controller signal the MSI vector with the number computed by taking the interrupter number modulo the number of enabled MSI vectors. This change introduces that modulo calculation, fixing the failed assertion. This makes the device work correctly in MSI mode with macOS's XHCI driver, which only allocates a single vector. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250112210056.16658-2-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/loongarch/virt: Checkpatch cleanupBibo Mao2025-01-133-6/+9
| | | | | | | | | | Code cleanup with directory hw/loongarch/, removing errors from command "scripts/checkpatch.pl hw/loongarch/*" Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250103064514.2660438-1-maobibo@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/hppa: Reset vCPUs calling resettable_reset()Helge Deller2025-01-131-3/+3
| | | | | | | | | | | Rather than manually (and incompletely) resetting vCPUs, call resettable_reset() which will fully reset the vCPUs. Remove redundant assignations. Signed-off-by: Helge Deller <deller@gmx.de> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241231190620.24442-4-philmd@linaro.org>
* hw/gpio/imx_gpio: Turn DPRINTF() into trace eventsBernhard Beschow2025-01-132-11/+12
| | | | | | | | | | While at it add a trace event for input GPIO events. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/i2c/imx_i2c: Convert DPRINTF() to trace eventsBernhard Beschow2025-01-132-16/+10
| | | | | | | | | | | Also print the QOM canonical path when tracing which allows for distinguishing the many instances a typical i.MX SoC has. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/char/imx_serial: Turn some DPRINTF() statements into trace eventsBernhard Beschow2025-01-132-19/+44
| | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-9-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/misc/imx6_src: Convert DPRINTF() to trace eventsBernhard Beschow2025-01-132-18/+11
| | | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/timer/imx_gpt: Remove unused defineBernhard Beschow2025-01-131-4/+0
| | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-11-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/char/stm32f2xx_usart: replace print with traceNikita Shubin2025-01-132-26/+29
| | | | | | | | | | Drop debug printing macros and replace them with according trace functions. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241220111756.16511-1-nikita.shubin@maquefel.me> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/sd/sdhci: Factor sdhci_sdma_transfer() outPhilippe Mathieu-Daudé2025-01-131-11/+11
| | | | | | | | | | Factor sdhci_sdma_transfer() out of sdhci_data_transfer(). Re-use it in sdhci_write(), so we don't try to run multi block transfer for a single block. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20250109122029.22780-1-philmd@linaro.org>
* hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriateBernhard Beschow2025-01-131-3/+8
| | | | | | | | | | | | In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and "DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU currently misses to set the DMA bit which causes the driver to loop forever. Fix that by setting the DMA bit if enabled when doing DMA block transfers. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/ufs: Adjust value to match CPU's endian formatKeoseong Park2025-01-131-1/+1
| | | | | | | | | | | | | | In ufs_write_attr_value(), the value parameter is handled in the CPU's endian format but provided in big-endian format by the caller. Thus, it is converted to the CPU's endian format. The related test code is also fixed to reflect this change. Fixes: 7c85332a2b3e ("hw/ufs: minor bug fixes related to ufs-test") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Keoseong Park <keosung.park@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Message-ID: <20250107084356epcms2p2af4d86432174d76ea57336933e46b4c3@epcms2p2> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/pci: Rename has_power to enabledAkihiko Odaki2025-01-132-8/+13
| | | | | | | | | | The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250109-reuse-v19-1-f541e82ca5f7@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/misc/vmcoreinfo: Convert to three-phase reset interfacePhilippe Mathieu-Daudé2025-01-131-3/+5
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241219153857.57450-6-philmd@linaro.org>
* hw/misc/vmcoreinfo: Rename VMCOREINFO_DEVICE -> TYPE_VMCOREINFOPhilippe Mathieu-Daudé2025-01-131-3/+3
| | | | | | | | | | Follow the assumed QOM type definition style, prefixing with 'TYPE_', and dropping the '_DEVICE' suffix which doesn't add any value. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20250102132624.53443-1-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map RESERVED I/O as unimplementedPhilippe Mathieu-Daudé2025-01-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to track access to reserved I/O space, use yet another UnimplementedDevice covering the whole device memory range. Mapped with lower priority (-1). The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000fe4-0000000081000ff3 (prio -1, i/o): ethlite.reserved @0000000000000fe4 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017e4-00000000810017fb (prio -1, i/o): ethlite.reserved @00000000000017e4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001fe4-0000000081001ffb (prio -1, i/o): ethlite.reserved @0000000000001fe4 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241114210010.34502-20-philmd@linaro.org>
* hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container'Philippe Mathieu-Daudé2025-01-131-8/+8
| | | | | | | | | | Having all its address range mapped by subregions, s->mmio MemoryRegion effectively became a container. Rename it as 'container' for clarity. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241112181044.92193-21-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory regionPhilippe Mathieu-Daudé2025-01-131-64/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than using I/O registers for RAM buffer, having to swap endianness back and forth (because the core memory layer automatically swaps endiannes for us), declare the buffers as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have any more I/O regions. Remove the now unused s->regs[] array. The memory flat view becomes: FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reported-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241114210010.34502-18-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map TX_CTRL as MMIOPhilippe Mathieu-Daudé2025-01-131-30/+24
| | | | | | | | | | | | | | | | | | | | | | | Add TX_CTRL to the TX registers MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000800 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001000 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-19-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map TX_GIE as MMIOPhilippe Mathieu-Daudé2025-01-131-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007fb (prio 0, i/o): ethlite.tx[0]io 00000000810007fc-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007fc 0000000081000ff4-0000000081000ffb (prio 0, i/o): ethlite.tx[1]io 0000000081000ffc-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ffc 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-18-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map TX_LEN as MMIOPhilippe Mathieu-Daudé2025-01-131-12/+61
| | | | | | | | | | | | | | | | | | | | | | | | Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007f7 (prio 0, i/o): ethlite.tx[0]io 00000000810007f8-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f8 0000000081000ff4-0000000081000ff7 (prio 0, i/o): ethlite.tx[1]io 0000000081000ff8-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ff8 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-17-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map RX_CTRL as MMIOPhilippe Mathieu-Daudé2025-01-131-15/+67
| | | | | | | | | | | | | | | | | | | | Declare RX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241112181044.92193-16-philmd@linaro.org>
* hw/net/xilinx_ethlite: Access TX_CTRL register for each portPhilippe Mathieu-Daudé2025-01-131-8/+7
| | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_CTRL. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-15-philmd@linaro.org>
* hw/net/xilinx_ethlite: Access TX_LEN register for each portPhilippe Mathieu-Daudé2025-01-131-2/+6
| | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_LEN. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-14-philmd@linaro.org>
* hw/net/xilinx_ethlite: Access TX_GIE register for each portPhilippe Mathieu-Daudé2025-01-131-2/+10
| | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-13-philmd@linaro.org>
* hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helperPhilippe Mathieu-Daudé2025-01-131-10/+29
| | | | | | | | | rxbuf_ptr() points to the beginning of a (RAM) RX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-11-philmd@linaro.org>
* hw/net/xilinx_ethlite: Introduce txbuf_ptr() helperPhilippe Mathieu-Daudé2025-01-131-2/+16
| | | | | | | | | | | | For a particular physical address within the EthLite MMIO range, addr_to_port_index() returns which port is accessed. txbuf_ptr() points to the beginning of a (RAM) TX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-10-philmd@linaro.org>
* hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented)Philippe Mathieu-Daudé2025-01-131-0/+12
| | | | | | | | | | | | | | | | | | Rather than handling the MDIO registers as RAM, map them as unimplemented I/O within the device MR. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-0000000081001fff (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-7-philmd@linaro.org>
* hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bitPhilippe Mathieu-Daudé2025-01-133-0/+12
| | | | | | | | | | All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20241105130431.22564-8-philmd@linaro.org>
* hw/qdev: Check machine_hotplug_handler in hotplug_unplug_allowed_commonAkihiko Odaki2025-01-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 03fcbd9dc508 ("qdev: Check for the availability of a hotplug controller before adding a device") says: > The qdev_unplug() function contains a g_assert(hotplug_ctrl) > statement, so QEMU crashes when the user tries to device_add + > device_del a device that does not have a corresponding hotplug > controller. > The code in qdev_device_add() already checks whether the bus has a > proper hotplug controller, but for devices that do not have a > corresponding bus, here is no appropriate check available yet. In that > case we should check whether the machine itself provides a suitable > hotplug controller and refuse to plug the device if none is available. However, it forgot to add the corresponding check to qdev_unplug(). Check the machine hotplug handler once in the common qdev_hotplug_unplug_allowed_common() helper so both hotplug and hot-unplug path are covered. Fixes: 7716b8ca74 ("qdev: HotplugHandler: Add support for unplugging BUS-less devices") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 6/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-7-philmd@linaro.org>
* hw/qdev: Check qbus_is_hotpluggable in hotplug_unplug_allowed_commonAkihiko Odaki2025-01-131-0/+8
| | | | | | | | | | Check the same code once in the common helper. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 5/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-6-philmd@linaro.org>
* hw/qdev: Check DevClass::hotpluggable in hotplug_unplug_allowed_commonAkihiko Odaki2025-01-131-0/+9
| | | | | | | | | | Check the same code once in the common helper. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 4/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-5-philmd@linaro.org>
* hw/qdev: Introduce qdev_hotplug_unplug_allowed_common()Akihiko Odaki2025-01-131-1/+12
| | | | | | | | | | | Introduce qdev_hotplug_unplug_allowed_common() to hold common code between checking hot-plug/unplug is allowed. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 3/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-4-philmd@linaro.org>
* hw/qdev: Factor qdev_hotunplug_allowed() outAkihiko Odaki2025-01-131-0/+5
| | | | | | | | | | | Factor qdev_hotunplug_allowed() out of qdev_unplug(). Start checking the device is not blocked. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 2/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-3-philmd@linaro.org>
* hw/qdev: Pass bus argument to qdev_hotplug_allowed()Akihiko Odaki2025-01-131-1/+1
| | | | | | | | | | | In preparation of checking the parent bus is hot(un)pluggable in a few commits, pass a 'bus' argument to qdev_hotplug_allowed(). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [PMD: Split from bigger patch, part 1/6] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250110091908.64454-2-philmd@linaro.org>
* hw/usb: Inline usb_new()Philippe Mathieu-Daudé2025-01-132-2/+3
| | | | | | | | Inline the 3 uses of usb_new(). Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240216110313.17039-11-philmd@linaro.org>
* hw/usb: Inline usb_try_new()Philippe Mathieu-Daudé2025-01-131-1/+1
| | | | | | | | Inline the single use of usb_try_new(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240216110313.17039-10-philmd@linaro.org>
* hw: Replace DEVICE(object_new) -> qdev_new()Philippe Mathieu-Daudé2025-01-132-3/+3
| | | | | | | | Prefer QDev API for QDev objects, avoid the underlying QOM layer. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240216110313.17039-7-philmd@linaro.org>
* target/arm: change default pauth algorithm to impdefPierrick Bouvier2025-01-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=on). The advice is always: use pauth-impdef=on. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we change the default to use impdef by default. This does not affect kvm or hvf acceleration, since pauth algorithm used is the one from host cpu. This change is retro compatible, in terms of cli, with previous versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu max,pauth-qarma3=on is preserved. The new option introduced in previous patch and matching old default is -cpu max,pauth-qarma5=on. It is retro compatible with migration as well, by defining a backcompat property, that will use qarma5 by default for virt machine <= 9.2. Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master (10.0) for cpus neoverse-n2 and max. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc: cast rpm to uint64_tTigran Sogomonian2025-01-131-2/+3
| | | | | | | | | | | | | | | | The value of an arithmetic expression 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject to overflow because its operands are not cast to a larger data type before performing arithmetic. Thus, need to cast rpm to uint64_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Tigran Sogomonian <tsogomonian@astralinux.ru> Reviewed-by: Patrick Leis <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20241226130311.1349-1-tsogomonian@astralinux.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm_sysctl: fix extracting 31th bit of valAnastasia Belova2025-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | 1 << 31 is casted to uint64_t while bitwise and with val. So this value may become 0xffffffff80000000 but only 31th "start" bit is required. This is not possible in practice because the MemoryRegionOps uses the default max access size of 4 bytes and so none of the upper bytes of val will be set, but the bitfield extract API is clearer anyway. Use the bitfield extract() API instead. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Anastasia Belova <abelova@astralinux.ru> Message-id: 20241220125429.7552-1-abelova@astralinux.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: add clarification to commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'migration-20250110-pull-request' of ↵Stefan Hajnoczi2025-01-101-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/farosas/qemu into staging Migration pull request - compression: Shameer's fix for CONFIG_UADK build Yuan Liu fixes for zero-page, QPL, qatzip - multifd sync cleanups, prereq. for VFIO and postcopy work - fixes for 9.2 regressions: multifd with pre-9.0 -> post-9.1 migrations (#2720) s390x migration (#2704) - fix for assertions during paused migrations; rework of late-block-activate logic (#2395, #686) - fixes for compressed arrays creation and parsing, mostly affecting s390x # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeBDgkQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnSlUEACl31wY+77JxWnBva/eDDwnJ9HiCrqsoqaZ # YIJJXNlk4lYJWNdZRt6p27exzWrQwm+kWKPECeCakgCMlfhnKCvejGq7iV/fJY4o # D8hjE3t1htQ8mfblY1+bqzg3Rml59KwXxiqAwvlljbNWdkXruv026dq9vgJMzFhi # ia043fOO1tYULIoawgmwmLEHnztht0v+ZTZ1v5KQbrH655tpxls/8kHc6v5PXEpA # 3PSmCrCQh1dPtkYRjuJ9yHyfU+/T8tYwIjrU6VR1wQW7MBNkjtqNudaqAFiuyuqn # P8gh4rAQrMhA9y+aq6xSoJP8XGkuOHxLQtlNutlmtbcQyZ7JqgLmK9ZLdoPf21sK # //erV63NoyaciYB9Nk3NXflwroc6zyvo8A584kGNPwBznZOJLESP4SPvVm/nlE29 # vbyq8AWHRjFiqqf6P0ttQLAFkusZJzM1Y9UakF51hyVBX70yfqLG20XXZtIq/aZA # GbBB2Fo0MIlbmWaur3vLsSzn7B8d++Gl9TTGcK/eIXJ1ANCuCxGv9fbXJQlP5F4I # 3OAoSmAVJ2eqw4v0+2WMiEa8yUA5drNnDSI3VRkG+0K9jRfHKXki466/QQdGrNw7 # 8GuuzLBNai3gEKbavDU0Be73r982KjXeYXj7RuAkQfm0d4H7tiwtg91Cd1dPKfzh # mhpmOFJDCg== # =joNM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Jan 2025 07:09:45 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250110-pull-request' of https://gitlab.com/farosas/qemu: (25 commits) multifd: bugfix for incorrect migration data with qatzip compression multifd: bugfix for incorrect migration data with QPL compression multifd: bugfix for migration using compression methods s390x: Fix CSS migration migration: Fix arrays of pointers in JSON writer migration: Dump correct JSON format for nullptr replacement migration: Rename vmstate_info_nullptr migration: Fix parsing of s390 stream migration: Remove unused argument in vmsd_desc_field_end migration: Add more error handling to analyze-migration.py migration/block: Rewrite disk activation migration/block: Fix possible race with block_inactive migration/block: Apply late-block-active behavior to postcopy migration/block: Make late-block-active the default qmp/cont: Only activate disks if migration completed migration: Add helper to get target runstate migration/multifd: Fix compat with QEMU < 9.0 migration/multifd: Document the reason to sync for save_setup() migration/multifd: Cleanup src flushes on condition check migration/multifd: Remove sync processing on postcopy ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>