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* Merge tag 'physmem-20251007' of https://github.com/philmd/qemu into stagingRichard Henderson2025-10-0720-33/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory patches - Cleanups on RAMBlock API - Cleanups on Physical Memory API - Remove cpu_physical_memory_is_io() - Remove cpu_physical_memory_rw() - Legacy conversion [cpu_physical_memory -> address_space]_[un]map() # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmjkgzUACgkQ4+MsLN6t # wN7ouQ//V/goGzlt3AueQCs3UwYLsnLbHq6PIlddEmbEe4VobgBMY6qhgvM54dhS # EX/uBikOVHNSjFzKTcr67fLk+wIaGpY6VeZWHibKTh9dFPGjPCBOshYRQl8Oe31p # 4sIppkJGcuvQyXO07avLoSbpUo7REDja1G688D45ANOEPpb+7nHJlgq7uWUlbT5k # ICqT6TF+V0nmM/4yK19sFdimyS++PtnAgLwdODhG6apMNy8CkjE2I6IaPFHaCJEf # +we8iHxhPn6NkP7P7EHDNkLAOz/jhL7pIf3/kC3Pc+aMtXYOrH1dVcmMhF9zbP/F # MXMQIOIhKbuEksqIpTqP80UegTO4WVBPPDNZafRtA3Fzfex5WU0PxbtrwZtSNCP4 # e5mSp36Xp2fLaAsXMZBIUQrRnj4Hy0m7YMFSi8aoMsJRvnou6cJ02BCWjP+VUk74 # rrGpHKZ3vIhwVsRVcU43m8Xctk0H9KkhOTVvOGqzBUnJUo2eQb7w4qUxim7L8EoP # g2AOak+wdwpi0402QFPf2PD1WKGu3kc3Kuny/C7YeIUdTrRR8wPCWsIjmusFRnFv # 1deZOlwVu4ESIuPiuHsLN7WbSZjEPxZH4cgUZmdeoKCTn6vNkC6FWlluMnS8Y+Bb # c3AKo9kVatznQvY/qiH8h8rYqI8RFta8F8QHoIo1t41YJKlzuOY= # =FLzC # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Oct 2025 08:04:21 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'physmem-20251007' of https://github.com/philmd/qemu: (41 commits) system/physmem: Extract API out of 'system/ram_addr.h' header system/physmem: Drop 'cpu_' prefix in Physical Memory API system/physmem: Reduce cpu_physical_memory_sync_dirty_bitmap() scope system/physmem: Reduce cpu_physical_memory_clear_dirty_range() scope system/physmem: Un-inline cpu_physical_memory_dirty_bits_cleared() system/physmem: Un-inline cpu_physical_memory_set_dirty_lebitmap() system/physmem: Remove _WIN32 #ifdef'ry system/physmem: Un-inline cpu_physical_memory_set_dirty_range() system/physmem: Un-inline cpu_physical_memory_set_dirty_flag() system/physmem: Un-inline cpu_physical_memory_range_includes_clean() system/physmem: Un-inline cpu_physical_memory_is_clean() system/physmem: Un-inline cpu_physical_memory_get_dirty_flag() hw: Remove unnecessary 'system/ram_addr.h' header target/arm/tcg/mte: Include missing 'exec/target_page.h' header hw/vfio/listener: Include missing 'exec/target_page.h' header hw/s390x/s390-stattrib: Include missing 'exec/target_page.h' header accel/kvm: Include missing 'exec/target_page.h' header system/ram_addr: Remove unnecessary 'exec/cpu-common.h' header hw/virtio/virtio: Replace legacy cpu_physical_memory_map() call hw/virtio/vhost: Replace legacy cpu_physical_memory_*map() calls ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * system/physmem: Extract API out of 'system/ram_addr.h' headerPhilippe Mathieu-Daudé2025-10-073-2/+2
| | | | | | | | | | | | | | | | | | | | Very few files use the Physical Memory API. Declare its methods in their own header: "system/physmem.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20251001175448.18933-19-philmd@linaro.org>
| * system/physmem: Drop 'cpu_' prefix in Physical Memory APIPhilippe Mathieu-Daudé2025-10-072-6/+6
| | | | | | | | | | | | | | | | | | | | | | The functions related to the Physical Memory API declared in "system/ram_addr.h" do not operate on vCPU. Remove the 'cpu_' prefix. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20251001175448.18933-18-philmd@linaro.org>
| * hw: Remove unnecessary 'system/ram_addr.h' headerPhilippe Mathieu-Daudé2025-10-078-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | None of these files require definition exposed by "system/ram_addr.h", remove its inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20251001175448.18933-7-philmd@linaro.org>
| * hw/vfio/listener: Include missing 'exec/target_page.h' headerPhilippe Mathieu-Daudé2025-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "exec/target_page.h" header is indirectly pulled from "system/ram_addr.h". Include it explicitly, in order to avoid unrelated issues when refactoring "system/ram_addr.h": hw/vfio/listener.c: In function ‘vfio_ram_discard_register_listener’: hw/vfio/listener.c:258:28: error: implicit declaration of function ‘qemu_target_page_size’; did you mean ‘qemu_ram_pagesize’? 258 | int target_page_size = qemu_target_page_size(); | ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20251001175448.18933-5-philmd@linaro.org>
| * hw/s390x/s390-stattrib: Include missing 'exec/target_page.h' headerPhilippe Mathieu-Daudé2025-10-072-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "exec/target_page.h" header is indirectly pulled from "system/ram_addr.h". Include it explicitly, in order to avoid unrelated issues when refactoring "system/ram_addr.h": hw/s390x/s390-stattrib-kvm.c: In function ‘kvm_s390_stattrib_set_stattr’: hw/s390x/s390-stattrib-kvm.c:89:57: error: ‘TARGET_PAGE_SIZE’ undeclared (first use in this function); did you mean ‘TARGET_PAGE_BITS’? 89 | unsigned long max = s390_get_memory_limit(s390ms) / TARGET_PAGE_SIZE; | ^~~~~~~~~~~~~~~~ | TARGET_PAGE_BITS Since "system/ram_addr.h" is actually not needed, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20251001175448.18933-4-philmd@linaro.org>
| * hw/virtio/virtio: Replace legacy cpu_physical_memory_map() callPhilippe Mathieu-Daudé2025-10-071-4/+6
| | | | | | | | | | | | | | | | | | | | Propagate VirtIODevice::dma_as to virtqueue_undo_map_desc() in order to replace the legacy cpu_physical_memory_unmap() call by address_space_unmap(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-18-philmd@linaro.org>
| * hw/virtio/vhost: Replace legacy cpu_physical_memory_*map() callsPhilippe Mathieu-Daudé2025-10-071-2/+5
| | | | | | | | | | | | | | | | | | Use VirtIODevice::dma_as address space to convert the legacy cpu_physical_memory_[un]map() calls to address_space_[un]map(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-17-philmd@linaro.org>
| * hw/xen/hvm: Inline cpu_physical_memory_rw() in rw_phys_req_item()Philippe Mathieu-Daudé2025-10-071-3/+5
| | | | | | | | | | | | | | | | cpu_physical_memory_rw() is legacy, replace by address_space_rw(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-13-philmd@linaro.org>
| * hw/s390x/sclp: Replace [cpu_physical_memory -> address_space]_r/w()Philippe Mathieu-Daudé2025-10-071-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | cpu_physical_memory_read() and cpu_physical_memory_write() are legacy (see commit b7ecba0f6f6), replace by address_space_read() and address_space_write(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20251002084203.63899-8-philmd@linaro.org>
| * system/physmem: Pass address space argument to cpu_flush_icache_range()Philippe Mathieu-Daudé2025-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | Rename cpu_flush_icache_range() as address_space_flush_icache_range(), passing an address space by argument. The single caller, rom_reset(), already operates on an address space. Use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-7-philmd@linaro.org>
| * hw/s390x/sclp: Use address_space_memory_is_io() in sclp_service_call()Philippe Mathieu-Daudé2025-10-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cpu_address_space_init() isn't called during vCPU creation, its single address space is the global &address_space_memory. As s390x boards don't call cpu_address_space_init(), cpu->as points to &address_space_memory. We can then replace cpu_physical_memory_is_io() by the semantically equivalent address_space_memory_is_io() call. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20251002084203.63899-5-philmd@linaro.org>
| * system/ramblock: Move ram_block_discard_*_range() declarationsPhilippe Mathieu-Daudé2025-10-073-0/+3
| | | | | | | | | | | | | | | | | | Keep RAM blocks API in the same header: "system/ramblock.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-4-philmd@linaro.org>
* | hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé2025-10-071-42/+0
| | | | | | | | | | | | | | | | | | | | | | | | When removing the spitz and tosa board, commit b62151489ae ("hw/arm: Remove deprecated akita, borzoi spitz, terrier, tosa boards") removed the last calls to sl_bootparam_write(). Remove it, along with the "hw/arm/sharpsl.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20251001084047.67423-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2025-10-071-1/+76
| | | | | | | | | | | | | | | | | | | | This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Clément Chigot <chigot@adacore.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-4-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-zynqmp: introduce helper to compute RPU numberClément Chigot2025-10-071-3/+12
| | | | | | | | | | | | | | | | | | | | This helper will avoid repeating the MIN/MAX formula everytime the number of RPUs available is requested. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-3-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2025-10-071-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | This define will be needed in a later patch in XlnxZynqMPState structure, hence move it within xlnx-zynqmp header. Add XLXN_ZYNQMP prefix as it's now public. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-2-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machineLuc Michel2025-10-071-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Versal Gen 2 Virtual development machine embedding a versal2 SoC. This machine follows the same principle than the xlnx-versal-virt machine. It creates its own DTB and feeds it to the software payload. This way only implemented devices are exposed to the guest and the user does not need to provide a DTB. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-47-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal-virt: tidy upLuc Michel2025-10-071-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove now unused clock nodes. They have been replaced by the ones created in the SoC. Remove the unused cfg.secure VersalVirt field. Remove unecessary include directives. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-44-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal-virt: split into base/concrete classesLuc Michel2025-10-071-22/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the xlnx-versal-virt machine type into a base abstract type and a concrete type. There is no functional change. This is in preparation for the versal2 machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-43-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virtLuc Michel2025-10-071-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-42-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add versal2 SoCLuc Michel2025-10-071-14/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Versal Gen 2 (versal2) version of the Versal SoC family. This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters) and 10 Cortex-R52 cores (split into 5 clusters). The similarities between versal and versal2 in term of architecture allow to reuse the VersalMap structure to almost fully describe the implemented parts of versal2. The versal2 eFuse device differs quite a lot from the versal one and is left as future work. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-41-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add the target field in IRQ descriptorLuc Michel2025-10-071-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the target field in the IRQ descriptor. This allows to target an IRQ to another IRQ controller than the GIC(s). Other supported targets are the PMC PPU1 CPU interrupt controller and the EAM (Error management) device. Those two devices are currently not implemented so IRQs targeting those will be left unconnected. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-39-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMapLuc Michel2025-10-071-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the per_cluster_gic switch to the VersalCpuClusterMap structure. When set, this indicates that a GIC instance should by created per-cluster instead of globally for the whole RPU or APU. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-38-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel2025-10-071-0/+392
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-37-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: tidy upLuc Michel2025-10-071-21/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove now unused macros in xlnx-versal.[ch]. Those macros have been replaced by the VersalMap structure that serves as a central description for the SoC. The ones still in use in the versal_unimp function are inlined. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-36-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2025-10-071-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the bsa.h header for ARM timer and maintainance IRQ indices instead of redefining our owns. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-35-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: reconnect the CRL to the other devicesLuc Michel2025-10-071-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CRL connects to various devices through link properties to be able to reset them. The connections were dropped during the SoC refactoring. Reintroduce them now. Rely on the QOM tree to retrieve the devices to connect. The component parts of the device names are chosen to match the properties on the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-34-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2025-10-071-75/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the device reset logic to have a common register write callback for all the devices. This uses a decode function to map the register address to the actual peripheral to reset. This refactoring changes the CPU property name from cpu_r5[*] to rpu[*] to ease with the connections in the Versal SoC. It also fixes a bug where the gem device pointer was mapped to the usb link property. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-33-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2025-10-071-19/+29
| | | | | | | | | | | | | | | | | | | | | | | | Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-32-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/misc/xlnx-versal-crl: remove unnecessary include directivesLuc Michel2025-10-071-4/+1
| | | | | | | | | | | | | | | | | | | | | | Drop unused include directives from xlnx-versal-crl.c Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-31-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel2025-10-072-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the number of CPUs in the SoC. Use it in the xlnx-versal-virt machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-30-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: ddr: refactor creationLuc Michel2025-10-072-101/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-29-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2025-10-071-4/+16
| | | | | | | | | | | | | | | | | | | | | | Refactor the OCM creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-28-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: rpu: refactor creationLuc Michel2025-10-072-35/+26
| | | | | | | | | | | | | | | | | | | | | | | | Refactor the RPU cluster creation using the VersalMap structure. This effectively instantiate the RPU GICv2 which was not instantiated before. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-27-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add support for GICv2Luc Michel2025-10-071-20/+62
| | | | | | | | | | | | | | | | | | | | | | | | Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-26-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2025-10-071-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-25-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias2025-10-073-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a 'first-cpu-index' property for specifying the first QEMU CPU connected to the GICv3. This makes it possible to have multiple instances of the GICv3 connected to different CPU clusters. For KVM, mark this property has unsupported. It probably does not make much sense as it is intented to be used to model non-SMP systems. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-24-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: instantiate the GIC ITS in the APULuc Michel2025-10-071-0/+50
| | | | | | | | | | | | | | | | | | | | | | Add the instance of the GIC ITS in the APU. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-23-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: add the mp_affinity property to the CPU mappingLuc Michel2025-10-071-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a way to configure the MP affinity value of the CPUs given their core and cluster IDs. For the Versal APU CPUs, the MP affinity value is given by the core ID in Aff0. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-22-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: refactor CPU cluster creationLuc Michel2025-10-072-160/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the CPU cluster creation using the VersalMap structure. There is no functional change. The clusters properties are now described in the VersalMap structure. For now only the APU is converted. The RPU will be taken care of by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-21-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal-virt: virtio: refactor creationLuc Michel2025-10-072-19/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the creation of virtio devices. Use the accessors provided by the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are defined in the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-20-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: crl: refactor creationLuc Michel2025-10-071-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the CRL device creation using the VersalMap structure. The connections to the RPU CPUs are temporarily removed and will be reintroduced with next refactoring commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-19-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: cfu: refactor creationLuc Michel2025-10-071-141/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the CFU device creation using the VersalMap structure. All users of the APB IRQ OR gate have now been converted. The OR gate device can be dropped. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-18-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: rtc: refactor creationLuc Michel2025-10-072-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the RTC device creation using the VersalMap structure. The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1 (addr error IRQ). This does not change the current behaviour since the RTC model does not implement those IRQs anyway. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-17-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: trng: refactor creationLuc Michel2025-10-071-8/+10
| | | | | | | | | | | | | | | | | | | | | | Refactor the TRNG device creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-16-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: bbram: refactor creationLuc Michel2025-10-072-36/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the BBRAM device creation using the VersalMap structure. Note that the corresponding FDT node is removed. It does not correspond to any real node in standard Versal DTBs. No matching drivers exist for it. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-15-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: PMC IOU SCLR: refactor creationLuc Michel2025-10-071-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the PMC IOU SLCR device creation using the VersalMap structure. This is the first user of a shared IRQ using an OR gate. The OSPI controller is reconnected to the SLCR. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-14-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQsLuc Michel2025-10-071-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the IRQ index in the VersalMap structure to turn it into a descriptor: - the lower 16 bits still represent the IRQ index - bit 18 is used to indicate a shared IRQ connected to a OR gate - bits 19 to 22 indicate the index on the OR gate. This allows to share an IRQ among multiple devices. An OR gate is created to connect the devices to the actual IRQ pin. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-13-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/xlnx-versal: ospi: refactor creationLuc Michel2025-10-072-87/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the OSPI controller creation using the VersalMap structure. Note that the connection to the PMC IOU SLCR is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-12-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>